Reconfigurable nanoscale logic cells : a comparison study. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Renaud Daviot (ICECS, 2009)

Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu; Renaud Daviot (ICECS, 2009)

Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu (NANOARCH, 2009)

Emerging Technologies and Nanoscale Computing Fabrics. - Ian O'Connor; Junchen Liu; Kotb Jabeur; Nataliya Yakymets; Renaud Daviot; David Navarro; Pierre-Emmanuel Gaillardon; Fabien Clermidy; Maimouna Amadou; Gabriela Nicolescu (VLSI-SoC, 2009)

Phase-change-memory-based storage elements for configurable logic. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Marina Reyboz; Giovanni Beneventi; Fabien Clermidy; Luca Perniola; Ian O'Connor (FPT, 2010)

Emerging memory technologies for reconfigurable routing in FPGA architecture. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Giovanni Betti Beneventi; Fabien Clermidy; Luca Perniola (ICECS, 2010)

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. - Ian O'Connor; Kotb Jabeur; David Navarro; Nataliya Yakymets; Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy (ICECS, 2010)

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. - Kotb Jabeur; David Navarro; Ian O'Connor; Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy (NANOARCH, 2010)

Can we go towards true 3-D architectures? - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Paul-Henry Morel; Jean-Philippe Noël; Fabien Clermidy; Ian O'Connor (DAC, 2011)

Evaluation of a crossbar multiplexer in a lithography-based nanowire technology. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy; Ian O'Connor (ISCAS, 2011)

Ultra-fine grain FPGAs: A granularity study. - Pierre-Emmanuel Gaillardon; M. Haykel Ben Jamaa; Fabien Clermidy; Ian O'Connor (NANOARCH, 2011)

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. - Santhosh Onkaraiah; Pierre-Emmanuel Gaillardon; Marina Reyboz; Fabien Clermidy; Jean-Michel Portal; Marc Bocquet; Christophe Muller (NANOARCH, 2011)

Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method. - Pierre-Emmanuel Gaillardon; Fabien Clermidy; Ian O'Connor; Junchen Liu; Maimouna Amadou; Gabriela Nicolescu (ACM J. Emerg. Technol. Comput. Syst., 2011)

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. - Shashikanth Bobba; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (NANOARCH, 2012)

GMS: Generic memristive structure for non-volatile FPGAs. - Pierre-Emmanuel Gaillardon; Davide Sacchetto; Shashikanth Bobba; Yusuf Leblebici; Giovanni De Micheli (VLSI-SoC, 2012)

3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS. - Perrine Batude; Thomas Ernst 005; Julien Arcamone; Gregory Arndt; Perceval Coudrain; Pierre-Emmanuel Gaillardon (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2013)

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DAC, 2013)

Towards structured ASICs using polarity-tunable Si nanowire transistors. - Pierre-Emmanuel Gaillardon; Michele De Marchi; Luca Gaetano Amarù; Shashikanth Bobba; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DAC, 2013)

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2013)

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Shashikanth Bobba; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2013)

A fast TCAD-based methodology for Variation analysis of emerging nano-devices. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Majid Yazdani; Giovanni De Micheli (DFTS, 2013)

3.5-D integration: A case study. - Shashikanth Bobba; Pierre-Emmanuel Gaillardon; Ciprian Seiculescu; Vasilis F. Pavlidis; Giovanni De Micheli (ISCAS, 2013)

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET. - Ogun Turkyilmaz; Fabien Clermidy; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2013)

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. - Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2013)

Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. - Pierre-Emmanuel Gaillardon; Hassan Ghasemzadeh 002; Giovanni De Micheli (LATW, 2013)

SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT. - Catherine Gasnier; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2013)

Efficient arithmetic logic gates using double-gate silicon nanowire FETs. - Luca Arnani; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NEWCAS, 2013)

A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. - Ibrahim Kazi; Pascal Meinerzhagen; Pierre-Emmanuel Gaillardon; Davide Sacchetto; Andreas Burg 001; Giovanni De Micheli (NEWCAS, 2013)

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Giovanni De Micheli (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Data compression via logic synthesis. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Andreas Burg 001; Giovanni De Micheli (ASP-DAC, 2014)

Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs. - Yu Bi; Pierre-Emmanuel Gaillardon; Xiaobo Sharon Hu; Michael T. Niemier; Jiann-Shiun Yuan; Yier Jin (ATS, 2014)

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DAC, 2014)

An efficient manipulation package for Biconditional Binary Decision Diagrams. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2014)

Advanced system on a chip design based on controllable-polarity FETs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Jian Zhang 067; Giovanni De Micheli (DATE, 2014)

Majority Logic Synthesis for Spin Wave Technology. - Odysseas Zografos; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Praveen Raghavan; Giovanni De Micheli (DSD, 2014)

A new basic logic structure for data-path computation (abstract only). - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2014)

Pattern-based FPGA logic block and clustering algorithm. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPL, 2014)

A high-performance low-power near-Vt RRAM-based FPGA. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPT, 2014)

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. - Xifan Tang; Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2014)

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements. - Odysseas Zografos; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2014)

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Giovanni De Micheli (ISVLSI, 2014)

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Majid Yazdani; Giovanni De Micheli (NANOARCH, 2014)

3D technologies for reconfigurable architectures. - Fabien Clermidy; O. Turkyimaz; Olivier Billoint; Pierre-Emmanuel Gaillardon (ReCoSoC, 2014)

Novel configurable logic block architecture exploiting controllable-polarity transistors. - Pierre-Emmanuel Gaillardon; Xifan Tang; Giovanni De Micheli (ReCoSoC, 2014)

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. - Shashikanth Bobba; Jie Zhang 007; Pierre-Emmanuel Gaillardon; H.-S. Philip Wong; Subhasish Mitra; Giovanni De Micheli (ACM J. Emerg. Technol. Comput. Syst., 2014)

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. - Ibrahim Kazi; Pascal Andreas Meinerzhagen; Pierre-Emmanuel Gaillardon; Davide Sacchetto; Yusuf Leblebici; Andreas Peter Burg; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. - Jian Zhang 067; Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Multiple Independent Gate FETs: How many gates do we need? - Luca Gaetano Amarù; Gage Hills; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (ASP-DAC, 2015)

A ultra-low-power FPGA based on monolithically integrated RRAMs. - Pierre-Emmanuel Gaillardon; Xifan Tang; Jury Sandrini; Maxime Thammasack; Somayyeh Rahimian Omam; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2015)

Fault modeling in controllable polarity silicon nanowire circuits. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2015)

A surface potential and current model for polarity-controllable silicon nanowire FETs. - Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ESSDERC, 2015)

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). - Pierre-Emmanuel Gaillardon; Gain Kim; Xifan Tang; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2015)

Accurate power analysis for near-Vt RRAM-based FPGA. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPL, 2015)

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino; Luca Gaetano Amarù; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2015)

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices. - Kaveh Shamsi; Yu Bi; Yier Jin; Pierre-Emmanuel Gaillardon; Michael T. Niemier; Xiaobo Sharon Hu (ICCD, 2015)

FPGA-SPICE: A simulation-based power estimation framework for FPGAs. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ICCD, 2015)

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams. - Anupam Chattopadhyay; Alessandro Littarru; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISMVL, 2015)

Exploiting Circuit Duality to Speed up SAT. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Alan Mishchenko; Maciej J. Ciesielski; Giovanni De Micheli (ISVLSI, 2015)

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. - Hassan Ghasemzadeh 002; Pierre-Emmanuel Gaillardon; J. Zhang; Giovanni De Micheli; Ernesto Sánchez 001; Matteo Sonza Reorda (ISVLSI, 2015)

A fast pruning technique for low-power inexact Circuit design. - Johan Broc; Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Jaume Joven Murillo; Krishna V. Palem; Giovanni De Micheli (LASCAS, 2015)

A study on buffer distribution for RRAM-based FPGA routing structures. - Somayyeh Rahimian Omam; Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (LASCAS, 2015)

NEM relay design with biconditional binary decision diagrams. - Winston Haaswijk; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2015)

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. - Pierre-Emmanuel Gaillardon; Edith Beigné; Suzanne Lesecq; Giovanni De Micheli (ACM J. Emerg. Technol. Comput. Syst., 2015)

New Logic Synthesis as Nanotechnology Enabler. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (Proc. IEEE, 2015)

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. - Pierre-Emmanuel Gaillardon; Xifan Tang; Gain Kim; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Majority-based synthesis for nanotechnologies. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2016)

An MIG-based compiler for programmable logic-in-memory architectures. - Mathias Soeken; Saeideh Shirinzadeh; Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Rolf Drechsler; Giovanni De Micheli (DAC, 2016)

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Robert Wille; Giovanni De Micheli (DATE, 2016)

The Programmable Logic-in-Memory (PLiM) computer. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Anne Siemon; Eike Linn; Rainer Waser; Anupam Chattopadhyay; Giovanni De Micheli (DATE, 2016)

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. - Saeideh Shirinzadeh; Mathias Soeken; Pierre-Emmanuel Gaillardon; Rolf Drechsler (DATE, 2016)

Optimizing Majority-Inverter Graphs with functional hashing. - Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2016)

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPGA, 2016)

Digital, analog and RF design opportunities of three-independent-gate transistors. - Pierre-Emmanuel Gaillardon; Mehdi Hasan; Anirban Saha; Luca Gaetano Amarù; Ross Walker 001; Berardi Sensale Rodriguez (ISCAS, 2016)

Notes on Majority Boolean Algebra. - Anupam Chattopadhyay; Luca Gaetano Amarù; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISMVL, 2016)

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. - Pierre-Emmanuel Gaillardon; Romain Magni; Luca Gaetano Amarù; Mehdi Hasan; Ross Walker 001; Berardi Sensale Rodriguez; Jean-Frédéric Christmann; Edith Beigné (LATS, 2016)

Inversion optimization in Majority-Inverter Graphs. - Eleonora Testa; Mathias Soeken; Odysseas Zografos; Luca Gaetano Amarù; Praveen Raghavan; Rudy Lauwereins; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2016)

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. - Jury Sandrini; Marios Barlas; Maxime Thammasack; Tugba Demirci; Michele De Marchi; Davide Sacchetto; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Emerging Technology-Based Design of Primitives for Hardware Security. - Yu Bi; Kaveh Shamsi; Jiann-Shiun Yuan; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Xunzhao Yin; Xiaobo Sharon Hu; Michael T. Niemier; Yier Jin (ACM J. Emerg. Technol. Comput. Syst., 2016)

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Giovanni De Micheli; Ernesto Sánchez 001; Matteo Sonza Reorda (ACM J. Emerg. Technol. Comput. Syst., 2016)

A Sound and Complete Axiomatization of Majority-n Logic. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Anupam Chattopadhyay; Giovanni De Micheli (IEEE Trans. Computers, 2016)

Majority-Inverter Graph: A New Paradigm for Logic Optimization. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Study on the Programming Structures for RRAM-Based FPGA Architectures. - Xifan Tang; Gain Kim; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Multi-level logic benchmarks: An exactness study. - Luca Gaetano Amarù; Mathias Soeken; Winston Haaswijk; Eleonora Testa; Patrick Vuillod; Jiong Luo; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

A novel basis for logic rewriting. - Winston Haaswijk; Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

Endurance management for resistive Logic-In-Memory computing architectures. - Saeideh Shirinzadeh; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Rolf Drechsler (DATE, 2017)

Wave pipelining for majority-based beyond-CMOS technologies. - Odysseas Zografos; A. De Meester; Eleonora Testa; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Luca Gaetano Amarù; Praveen Raghavan; Francky Catthoor; Rudy Lauwereins (DATE, 2017)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Enabling exact delay synthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon; Janet Olson; Robert K. Brayton; Giovanni De Micheli (ICCAD, 2017)

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. - Mahesh Nataraj; Alexandre Levisse; Bastien Giraud; Jean-Philippe Noël; Pascal Andreas Meinerzhagen; Jean-Michel Portal; Pierre-Emmanuel Gaillardon (ISCAS, 2017)

An efficient electronic measurement interface for memristive biosensors. - Sebastien Naus; Ioulia Tzouvadaki; Pierre-Emmanuel Gaillardon; Armando Biscontini; Giovanni De Micheli; Sandro Carrara (ISCAS, 2017)

RM3 based logic synthesis (Special session paper). - Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2017)

Physical Design Considerations of One-level RRAM-based Routing Multiplexers. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ISPD, 2017)

Optimization opportunities in RRAM-based FPGA architectures. - Xifan Tang; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (LASCAS, 2017)

Low-power multiplexer designs using three-independent-gate field effect transistors. - Edouard Giacomin; Jorge Romero Gonzalez; Pierre-Emmanuel Gaillardon (NANOARCH, 2017)

Memristive logic: A framework for evaluation and comparison. - John Reuben; Rotem Ben Hur; Nimrod Wald; Nishil Talati; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (PATMOS, 2017)

A PLiM Computer for the Internet of Things. - Mathias Soeken; Pierre-Emmanuel Gaillardon; Saeideh Shirinzadeh; Rolf Drechsler; Giovanni De Micheli (Computer, 2017)

Exact Synthesis of Majority-Inverter Graphs and Its Applications. - Mathias Soeken; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers. - Xifan Tang; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Emerg. Top. Comput., 2017)

Towards high-performance polarity-controllable FETs with 2D materials. - Giovanni V. Resta; Jorge Romero Gonzalez; Yashwanth Balaji; Tarun Agarwal; Dennis Lin; Francky Catthoor; Iuliana P. Radu; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (DATE, 2018)

Practical challenges in delivering the promises of real processing-in-memory machines. - Nishil Talati; Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (DATE, 2018)

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. - Giovanni V. Resta; Yashwanth Balaji; Dennis Lin; Iuliana P. Radu; Francky Catthoor; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DRC, 2018)

Emerging reconfigurable nanotechnologies: can they support future electronics? - Shubham Rai; Srivatsa Rangachar Srinivasa; Patsy Cadareanu; Xunzhao Yin; Xiaobo Sharon Hu; Pierre-Emmanuel Gaillardon; Vijaykrishnan Narayanan; Akash Kumar 001 (ICCAD, 2018)

An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors. - Jorge Romero Gonzalez; Pierre-Emmanuel Gaillardon (ICRC, 2018)

Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. - Edouard Giacomin; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2018)

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Logic Synthesis for RRAM-Based In-Memory Computing. - Saeideh Shirinzadeh; Mathias Soeken; Pierre-Emmanuel Gaillardon; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Guest Editorial Memristive-Device-Based Computing. - Said Hamdioui; Pierre-Emmanuel Gaillardon; Dietmar Fey; Tajana Simunic Rosing (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Taxonomy and Evaluation Framework for Memristive Logic. - John Reuben; Nishil Talati; Nimrod Wald; Rotem Ben Hur; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (Handbook of Memristor Networks, 2019)

Memory Effects in Multi-terminal Solid State Devices and Their Applications. - Davide Sacchetto; Pierre-Emmanuel Gaillardon; Yusuf Leblebici; Giovanni De Micheli (Handbook of Memristor Networks, 2019)

Rebooting Our Computing Models. - Patsy Cadareanu; N. Reddy C; Carmen G. Almudéver; A. Khanna; Arijit Raychowdhury; Suman Datta; Koen Bertels; Vijayakrishan Narayanan; Massimiliano Di Ventra; Pierre-Emmanuel Gaillardon (DATE, 2019)

Scalable Boolean Methods in a Modern Synthesis Flow. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Jiong Luo; Christopher Casares; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2019)

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. - Xifan Tang; Edouard Giacomin; Aurélien Alacchi; Baudouin Chauviere; Pierre-Emmanuel Gaillardon (FPL, 2019)

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. - Walter Lau Neto; Max Austin; Scott Temple; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (ICCAD, 2019)

A Recursive Approach to Partially Blind Calibration of a Pollution Sensor Network. - Thomas Becnel; Tofigh Sayahi; Kerry E. Kelly; Pierre-Emmanuel Gaillardon (ICESS, 2019)

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. - Xifan Tang; Edouard Giacomin; Aurélien Alacchi; Pierre-Emmanuel Gaillardon (FPT, 2019)

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. - Walter Lau Neto; Xifan Tang; Max Austin; Luca G. Amarù; Pierre-Emmanuel Gaillardon (ISVLSI, 2019)

Wire-Aware Architecture and Dataflow for CNN Accelerators. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. - Anirban Nag; C. N. Ramachandra; Rajeev Balasubramonian; Ryan Stutsman; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

Functionality Enhanced Memories for Edge-AI Embedded Systems. - Alexandre Levisse; Marco Rios; William Andrew Simon; Pierre-Emmanuel Gaillardon; David Atienza (NVMTS, 2019)

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. - Ganesh Gore; Patsy Cadareanu; Edouard Giacomin; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2019)

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2019)

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2019)

A Distributed Low-Cost Pollution Monitoring Platform. - Thomas Becnel; Kyle Tingey; Jonathan Whitaker; Tofigh Sayahi; Katrina Lê; Pascal Goffin; Anthony Butterfield; Kerry E. Kelly; Pierre-Emmanuel Gaillardon (IEEE Internet Things J., 2019)

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. - Edouard Giacomin; Tzofnat Greenberg-Toledo; Shahar Kvatinsky; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. - Giovanni V. Resta; Alessandra Leonhardt; Yashwanth Balaji; Stefan De Gendt; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2019)

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Scalable Mixed Synthesis Framework for Heterogeneous Networks. - Max Austin; Scott Temple; Walter Lau Neto; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (DATE, 2020)

A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks. - Mohammad Mehdi Sharifi; Ramin Rajaei; Patsy Cadareanu; Pierre-Emmanuel Gaillardon; Yier Jin; Michael T. Niemier; Xiaobo Sharon Hu (DATE, 2020)

A RRAM-based FPGA for Energy-efficient Edge Computing. - Xifan Tang; Edouard Giacomin; Patsy Cadareanu; Ganesh Gore; Pierre-Emmanuel Gaillardon (DATE, 2020)

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. - Surya Narayanan; Karl Taht; Rajeev Balasubramonian; Edouard Giacomin; Pierre-Emmanuel Gaillardon (ISCA, 2020)

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SOC, 2020)

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2020)

Extending Boolean Methods for Scalable Logic Synthesis. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Access, 2020)

Exact Benchmark Circuits for Logic Synthesis. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; Pierre-Emmanuel Gaillardon; André Inácio Reis; Renato Perez Ribas (IEEE Des. Test, 2020)

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. - Xifan Tang; Edouard Giacomin; Baudouin Chauviere; Aurélien Alacchi; Pierre-Emmanuel Gaillardon (IEEE Micro, 2020)

NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. - Grant Brown; Valerio Tenace; Pierre-Emmanuel Gaillardon (ASAP, 2021)

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. - Walter Lau Neto; Matheus Trevisan Moreira; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (ASP-DAC, 2021)

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. - Walter Lau Neto; Matheus T. Moreira; Yingjie Li; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (DAC, 2021)

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. - Scott Temple; Walter Lau Neto; Ashton Snelgrove; Xifan Tang; Pierre-Emmanuel Gaillardon (DAC, 2021)

A Deep Learning Approach to Sensor Fusion Inference at the Edge. - Thomas Becnel; Pierre-Emmanuel Gaillardon (DATE, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. - Xifan Tang; Ganesh Gore; Grant Brown; Pierre-Emmanuel Gaillardon (FPL, 2021)

Exploring eFPGA-based Redaction for IP Protection. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (ICCAD, 2021)

Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. - Aurélien Alacchi; Edouard Giacomin; Xifan Tang; Pierre-Emmanuel Gaillardon (ISCAS, 2021)

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. - Edouard Giacomin; Francky Catthoor; Pierre-Emmanuel Gaillardon (ISCAS, 2021)

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. - Ganesh Gore; Xifan Tang; Pierre-Emmanuel Gaillardon (ISPD, 2021)

A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. - Matthieu Couriol; Patsy Cadareanu; Edouard Giacomin; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2021)

A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. - Matthieu Couriol; Patsy Cadareanu; Edouard Giacomin; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2021)

A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. - Matthieu Couriol; Edouard Giacomin; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2021)

Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. - Sherief Reda; Leon Stok; Pierre-Emmanuel Gaillardon (IEEE Des. Test, 2021)

multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. - Adi Eliahu; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (ACM J. Emerg. Technol. Comput. Syst., 2021)

Tiny Time-Series Transformers: Realtime Multi-Target Sensor Inference At The Edge. - Thomas Becnel; Kerry E. Kelly; Pierre-Emmanuel Gaillardon (COINS, 2022)

Improving LUT-based optimization for ASICs. - Walter Lau Neto; Luca G. Amarù; Vinicius Possani; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon (DAC, 2022)

ALICE: an automatic design flow for eFPGA redaction. - Chiara Muscari Tomajoli; Luca Collini; Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (DAC, 2022)

Programmable logic elements using multigate ambipolar transistors. - Ashton Snelgrove; Pierre-Emmanuel Gaillardon (DDECS, 2022)

An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. - Roman Gauchi; Ashton Snelgrove; Pierre-Emmanuel Gaillardon (ISCAS, 2022)

An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. - Michael Keyser; Roman Gauchi; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2022)

End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. - Walter Lau Neto; Yingjie Li; Pierre-Emmanuel Gaillardon; Cunxi Yu (CoRR, 2022)

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. - Gabriel Ammes; Walter Lau Neto; Paulo F. Butzen; Pierre-Emmanuel Gaillardon; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Programmable Local Clock SET Filtering for SEE-Resistant FPGA. - Aurélien Alacchi; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

University of Utah AirU Pollution Monitoring Network - Salt Lake City UT - 2019-07-26 - 2021-05-14. - Thomas Becnel; Kerry E. Kelly; Pierre-Emmanuel Gaillardon (IEEE DataPort, 2022)

Open-source and FPGAs: Hardware, Software, Both or None? - Dana How; Tim Ansell; Vaughn Betz; Chris Lavin; Ted Speers; Pierre-Emmanuel Gaillardon (FPGA, 2023)

Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs. - Grant Brown; Ganesh Gore; Pierre-Emmanuel Gaillardon (ISVLSI, 2023)

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. - Matthew Guthaus; Christopher Batten; Erik Brunvand; Pierre-Emmanuel Gaillardon; David M. Harris; Rajit Manohar; Pinaki Mazumder; Larry T. Pileggi; James E. Stine (CoRR, 2023)

Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. - Aurélien Alacchi; Edouard Giacomin; Scott Temple; Roman Gauchi; Michael J. Wirthlin; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. - Walter Lau Neto; Yingjie Li; Pierre-Emmanuel Gaillardon; Cunxi Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. - Aurélien Alacchi; Edouard Giacomin; Roman Gauchi; Szymon Kulis; Pierre-Emmanuel Gaillardon (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. - Ganesh Gore; Xifan Tang; Pierre-Emmanuel Gaillardon (IEEE Trans. Very Large Scale Integr. Syst., 2023)

CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. - Aman Arora 001; Atharva Bhamburkar; Aatman Borda; Tanmay Anand; Rishabh Sehgal; Bagus Hanindhito; Pierre-Emmanuel Gaillardon; Jaydeep Kulkarni; Lizy K. John (ACM Trans. Reconfigurable Technol. Syst., 2023)

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Secure eFPGA Configuration: A System-Level Approach. - Allen Boston; Roman Gauchi; Pierre-Emmanuel Gaillardon (ARC, 2024)

Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. - Seyed Mohammad Ali Zeinolabedin; Matthieu Couriol; Pierre-Emmanuel Gaillardon (MWSCAS, 2024)

Benchmarking Microfluidic Design Automation Flows. - Ashton Snelgrove; Skylar Stockham; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2024)

AIvril: AI-Driven RTL Generation With Verification In-The-Loop. - Mubashir ul Islam; Humza Sami; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2024)

EDA-Aware RTL Generation with Large Language Models. - Mubashir ul Islam; Humza Sami; Pierre-Emmanuel Gaillardon; Valerio Tenace (DATE, 2025)

OpenMFDA: Microfluidic Design Automation in Three Dimensions. - Ashton Snelgrove; Daniel Wakeham; Skylar Stockham; Scott Temple; Pierre-Emmanuel Gaillardon (DATE, 2025)

Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation. - Humza Sami; Mubashir ul Islam; Samy Charas; Asav Gandhi; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2025)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (CoRR, 2025)

Adaptive Multi-Agent Reasoning via Automated Workflow Generation. - Humza Sami; Mubashir ul Islam; Pierre-Emmanuel Gaillardon; Valerio Tenace (CoRR, 2025)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (ACM Trans. Design Autom. Electr. Syst., 2025)