Zero capacitor embedded memory technology for system on chip. - Serguei Okhonin; Pierre Fazan; Mark-Eric Jones (MTDT, 2005)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs. - Eddy Simoen; Marc Aoulaiche; Anabela Veloso; M. Jurczak; Cor Claeys; L. Mendes Almeida; Maria Glória Caño de Andrade; A. Luque Rodriguez; J. A. Jimenez Tejada; Christian Caillat; Pierre Fazan (ESSDERC, 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Off-state stress degradation mechanism on advanced p-MOSFETs. - Moonju Cho; Alessio Spessot; Ben Kaczer; Marc Aoulaiche; Romain Ritzenthaler; Tom Schram; Pierre Fazan; Naoto Horiguchi; Dimitri Linten (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. - Alessio Spessot; Romain Ritzenthaler; Tom Schram; Marc Aoulaiche; Moonju Cho; Maria Toledano-Luque; Naoto Horiguchi; Pierre Fazan (ICICDT, 2015)

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. - Barry J. O'Sullivan; Romain Ritzenthaler; Gerhard Rzepa; Z. Wu; E. Dentoni Litta; O. Richard; T. Conard; V. Machkaoutsan; Pierre Fazan; C. Kim; Jacopo Franco; Ben Kaczer; et al. (IRPS, 2019)

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery. - J. P. Bastos; Barry J. O'Sullivan; Jacopo Franco; Stanislav Tyaginov; Brecht Truijen; Adrian Vaisman Chasin; Robin Degraeve; Ben Kaczer; Romain Ritzenthaler; Elena Capogreco; E. Dentoni Litta; Alessio Spessot; et al. (IRPS, 2022)

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. - Romain Ritzenthaler; Elena Capogreco; E. Dupuy; Hiroaki Arimura; J. P. Bastos; P. Favia; F. Sebaai; D. Radisic; V. T. H. Nguyen; G. Mannaert; B. T. Chan; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2022)