Hardware Engines for Bus Encryption: A Survey of Existing Techniques. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; C. Anguille; Michel Bardouillet; Christian Buatois; Jean-Baptiste Rigaud (DATE, 2005)

A parallelized way to provide data encryption and integrity checking on a processor-memory bus. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (DAC, 2006)

PE-ICE: Parallelized Encryption and Integrity Checking Engine. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet (DDECS, 2006)

A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (PATMOS, 2006)

Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (ReCoSoC, 2006)

TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks. - Reouven Elbaz; David Champagne; Ruby B. Lee; Lionel Torres; Gilles Sassatelli; Pierre Guillemin (CHES, 2007)

SecBus: Operating System controlled hierarchical page-based memory bus protection. - Lifeng Su; Stephan Courcambeck; Pierre Guillemin; Christian Schwarz; Renaud Pacalet (DATE, 2009)

Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (Trans. Comput. Sci., 2010)