Modeling and Power Evaluation of On-Chip Router Components in Spintronics. - Pierre Schamberger; Zhonghai Lu; Xianyang Jiang; Meikang Qiu (NOCS, 2012)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. - Martin Cochet; Sylvain Clerc; Mehdi Naceur; Pierre Schamberger; Damien Croain; Jean-Luc Autran; Philippe Roche (ISCAS, 2016)