Compilation de programmes VHDL en vue de l'évaluation de testabilité d'équipements digitaux. (Compilation of VHDL programs for analysing testability of asynchronous digital devices). - Pierre Wodey (1993)

Linking Codesign and Verification by Means of E-LOTOS FDT. - Pierre Wodey; Fabrice Baray (EUROMICRO, 1999)

LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect. - Pierre Wodey; Geoffrey Camarroque; Fabrice Baray; Richard Hersemeule; Jean-Philippe Cousin (MEMOCODE, 2003)