Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures. - Mohamed Lamine Karaoui; Pierre-Yves Peneau; Quentin L. Meunier; Franck Wajsbürt; Alain Greiner (MCSoC, 2016)

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs. - Pierre-Yves Peneau; Rabab Bouziane; Abdoulaye Gamatié; Erven Rohou; Florent Bruguier; Gilles Sassatelli; Lionel Torres; Sophiane Senni (PATMOS, 2016)

Embedded systems to high performance computing using STT-MRAM. - Sophiane Senni; Thibaud Delobelle; Odilia Coi; Pierre-Yves Peneau; Lionel Torres; Abdoulaye Gamatié; Pascal Benoit; Gilles Sassatelli (DATE, 2017)

Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy. - Pierre-Yves Péneau; David Novo; Florent Bruguier; Lionel Torres; Gilles Sassatelli; Abdoulaye Gamatié (ARCS, 2018)

Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique. (Integration of emerging non volatile memory in the cache hierarchy for energy-efficiency improvement). - Pierre-Yves Péneau (2018)

NOP-Oriented Programming: Should we Care? - Pierre-Yves Péneau; Ludovic Claudepierre; Damien Hardy; Erven Rohou (EuroS&P Workshops, 2020)

TRAITOR: A Low-Cost Evaluation Platform for Multifault Injection. - Ludovic Claudepierre; Pierre-Yves Péneau; Damien Hardy; Erven Rohou (ASSS@AsiaCCS, 2021)