On the relationship between the CMRR or PSRR and the second harmonic distortion of differential input amplifiers. - Frank Op't Eynde; Piet Wambacq; Willy Sansen (IEEE J. Solid State Circuits, 1989)

Interactive symbolic distortion analysis of analogue integrated circuits. - Piet Wambacq; Georges G. E. Gielen; Willy Sansen (EURO-DAC, 1991)

Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. - Francisco V. Fernández 001; Piet Wambacq; Georges G. E. Gielen; Ángel Rodríguez-Vázquez; Willy M. C. Sansen (ISCAS, 1994)

Symbolic analysis methods and applications for analog circuits: a tutorial overview. - Georges G. E. Gielen; Piet Wambacq; Willy M. C. Sansen (Proc. IEEE, 1994)

Use of Symbolic Analysis in Analog Circuit Synthesis. - Georges G. E. Gielen; Geert Debyser; Piet Wambacq; Koen Swings; Willy M. C. Sansen (ISCAS, 1995)

Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits. - Piet Wambacq; Francisco V. Fernández 001; Georges G. E. Gielen; Willy Sansen; Ángel Rodríguez-Vázquez (IEEE J. Solid State Circuits, 1995)

A Single-Package Solution for Wireless Transceivers. - Piet Wambacq; Stéphane Donnay; Hocine Ziad; Marc Engels; Hugo De Man; Ivo Bolsens (DATE, 1999)

High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. - Piet Wambacq; Gerd Vandersteen; Stéphane Donnay; Marc Engels; Ivo Bolsens; Erik Lauwers; Piet Vanassche; Georges G. E. Gielen (ICECS, 1999)

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. - Gerd Vandersteen; Piet Wambacq; Yves Rolain; Petr Dobrovolný; Stéphane Donnay; Marc Engels; Ivo Bolsens (DAC, 2000)

Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. - Piet Wambacq; Petr Dobrovolný; Stéphane Donnay; Marc Engels; Ivo Bolsens (DATE, 2000)

Analysis and experimental verification of digital substrate noise generation for epi-type substrates. - Marc van Heijningen; John Compiet; Piet Wambacq; Stéphane Donnay; Marc Engels; Ivo Bolsens (IEEE J. Solid State Circuits, 2000)

Chip-package codesign of a low-power 5-GHz RF front end. - Stéphane Donnay; Philip Pieters; Kristof Vaesen; Wim Diels; Piet Wambacq; Walter De Raedt; Eric Beyne; Marc Engels; Ivo Bolsens (Proc. IEEE, 2000)

Efficient bit-error-rate estimation of multicarrier transceivers. - Gerd Vandersteen; Piet Wambacq; Yves Rolain; Johan Schoukens; Stéphane Donnay; Marc Engels; Ivo Bolsens (DATE, 2001)

CAD for RF circuits. - Piet Wambacq; Gerd Vandersteen; Joel R. Phillips; Jaijeet S. Roychowdhury; Wolfgang Eberle; Baolin Yang; David E. Long; Alper Demir 001 (DATE, 2001)

A Mixed-Signal Design Roadmap. - Ralf Brederlow; Werner Weber; Joseph Sauerer; Stéphane Donnay; Piet Wambacq; Maarten Vertregt (IEEE Des. Test Comput., 2001)

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. - Mustafa Badaroglu; Kris Tiri; Stéphane Donnay; Piet Wambacq; Hugo De Man; Ingrid Verbauwhede; Georges G. E. Gielen (DAC, 2002)

Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . - Michaël Goffioul; Piet Wambacq; Gerd Vandersteen; Stéphane Donnay (DATE, 2002)

High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. - Gerd Vandersteen; Piet Wambacq; Stéphane Donnay; Frans Verbeyst (DATE, 2002)

Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. - Petr Dobrovolný; Gerd Vandersteen; Piet Wambacq; Stéphane Donnay (DATE, 2003)

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. - Wolfgang Eberle; Gerd Vandersteen; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DATE, 2003)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Lakshmanan Balasubramanian; Kris Tiri; Vincent Gravot; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ESSCIRC, 2003)

A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology. - Manuel Innocent; Piet Wambacq; Stéphane Donnay; Willy Sansen; Hugo De Man (ESSCIRC, 2003)

Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. - Petr Dobrovolný; Gerd Vandersteen; Piet Wambacq; Stéphane Donnay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

An analytic Volterra-series-based model for a MEMS variable capacitor. - Manuel Innocent; Piet Wambacq; Stéphane Donnay; Harrie A. C. Tilmans; Willy M. C. Sansen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (CICC, 2004)

A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. - Dimitri Linten; Xiao Sun; Geert Carchon; Wutthinan Jeamsaksiri; Abdelkarim Mercha; Javier Ramos; Snezana Jenei; Lars Aspemyr; Andries J. Scholten; Piet Wambacq; Stefaan Decoutere; Stéphane Donnay; et al. (CICC, 2004)

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. - Geert Van der Plas; Mustafa Badaroglu; Gerd Vandersteen; Petr Dobrovolný; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DAC, 2004)

Digital Ground Bounce Reduction by Phase Modulation of the Clock. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DATE, 2004)

Performance degradation of an LC-tank VCO by impact of digital switching noise. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (ESSCIRC, 2004)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Lakshmanan Balasubramanian; Kris Tiri; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2004)

Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors. - Dimitri Linten; Xiao Sun; Steven Thijs; M. I. Natarajan; Abdelkarim Mercha; Geert Carchon; Piet Wambacq; Takeshi Nakaie; Stefaan Decoutere (CICC, 2005)

Substrate noise immune design of an LC-tank VCO using sensitivity functions. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (CICC, 2005)

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (DATE, 2005)

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. - Dimitri Linten; Xiao Sun; Geert Carchon; Wutthinan Jeamsaksiri; Abdelkarim Mercha; Javier Ramos; Snezana Jenei; Piet Wambacq; Morin Dehan; Lars Aspemyr; Andries J. Scholten; Stefaan Decoutere; et al. (IEEE J. Solid State Circuits, 2005)

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. - Dimitri Linten; Steven Thijs; Mahadeva Iyer Natarajan; Piet Wambacq; Wutthinan Jeamsaksiri; Javier Ramos; Abdelkarim Mercha; Snezana Jenei; Stéphane Donnay; Stefaan Decoutere (IEEE J. Solid State Circuits, 2005)

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Maarten Kuijk (IEEE J. Solid State Circuits, 2005)

ESD-RF co-design methodology for the state of the art RF-CMOS blocks. - Vesselin K. Vassilev; Steven Thijs; P. L. Segura; Piet Wambacq; Paul Leroux; Guido Groeseneken; M. I. Natarajan; Herman E. Maes; Michiel Steyaert (Microelectron. Reliab., 2005)

Digital ground bounce reduction by supply current shaping and clock frequency Modulation. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. - Julien Ryckaert; Claude Desset; Andrew Fort; Mustafa Badaroglu; Vincent De Heyn; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Bart van Poucke; Bert Gyselinckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges. - Stefaan Decoutere; Piet Wambacq; Vaidy Subramanian; Jonathan Borremans; Abdelkarim Mercha (CICC, 2006)

Body Area UWB RAKE Receiver Communication. - Andrew Fort; Claude Desset; Piet Wambacq; Leo Van Biesen (ICC, 2006)

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. - Julien Ryckaert; Mustafa Badaroglu; Vincent De Heyn; Geert Van der Plas; Pierluigi Nuzzo 001; Andrea Baschirotto; Stefano D'Amico; Claude Desset; Hans Suys; Michael Libois; Bart van Poucke; Piet Wambacq; et al. (ISSCC, 2006)

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. - Mustafa Badaroglu; Claude Desset; Julien Ryckaert; Vincent De Heyn; Geert Van der Plas; Piet Wambacq; Bart van Poucke (EURASIP J. Wirel. Commun. Netw., 2006)

Ultra-wideband channel model for communication around the human body. - Andrew Fort; Julien Ryckaert; Claude Desset; Philippe De Doncker; Piet Wambacq; Leo Van Biesen (IEEE J. Sel. Areas Commun., 2006)

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. - Charlotte Soens; Geert Van der Plas; Mustafa Badaroglu; Piet Wambacq; Stéphane Donnay; Yves Rolain; Maarten Kuijk (IEEE J. Solid State Circuits, 2006)

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. - Mustafa Badaroglu; Kris Tiri; Geert Van der Plas; Piet Wambacq; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Evolution of substrate noise generation mechanisms with CMOS technology scaling. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

SWAN: high-level simulation methodology for digital substrate noise generation. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. - Jonathan Borremans; Ludwig De Locht; Piet Wambacq; Yves Rolain (DATE, 2007)

Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis. - Pieter Crombez; Jan Craninckx; Piet Wambacq; Michiel Steyaert (ECCTD, 2007)

A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. - Jonathan Borremans; Piet Wambacq; Geert Van der Plas; Yves Rolain; Maarten Kuijk (ESSCIRC, 2007)

Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. - Andrew Fort; Mike Shuo-Wei Chen; Robert W. Brodersen; Claude Desset; Piet Wambacq; Leo Van Biesen (ICC, 2007)

FinFET technology for analog and RF circuits. - Bertrand Parvais; Vaidyanathan Subramanian; Abdelkarim Mercha; Morin Dehan; Piet Wambacq; Willy Sansen; Guido Groeseneken; Stefaan Decoutere (ICECS, 2007)

Scalable Gate-Level Models for Power and Timing Analysis. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ISCAS, 2007)

An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS. - Jonathan Borremans; Piet Wambacq; Dimitri Linten (ISSCC, 2007)

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. - Liesbet Van der Perre; Bruno Bougard; Jan Craninckx; Wim Dehaene; Lieven Hollevoet; Murali Jayapala; Pol Marchal; Miguel Miranda; Praveen Raghavan; Thomas Schuster; Piet Wambacq; Francky Catthoor; et al. (ISSCC, 2007)

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. - Julien Ryckaert; Marian Verhelst; Mustafa Badaroglu; Stefano D'Amico; Vincent De Heyn; Claude Desset; Pierluigi Nuzzo 001; Bart van Poucke; Piet Wambacq; Andrea Baschirotto; Wim Dehaene; Geert Van der Plas (IEEE J. Solid State Circuits, 2007)

The Potential of FinFETs for Analog and RF Circuit Applications. - Piet Wambacq; Bob Verbruggen; Karen Scheir; Jonathan Borremans; Morin Dehan; Dimitri Linten; Vincent De Heyn; Geert Van der Plas; Abdelkarim Mercha; Bertrand Parvais; Cedric Gustin; Vaidyanathan Subramanian; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. - Steven Thijs; Mototsugu Okushima; Jonathan Borremans; Philippe Jansen; Dimitri Linten; Mirko Scholz; Piet Wambacq; Guido Groeseneken (CICC, 2008)

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. - Jonathan Borremans; Julien Ryckaert; Piet Wambacq; Maarten Kuijk; Jan Craninckx (ESSCIRC, 2008)

A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS. - Jonathan Borremans; Stephane Bronckers; Piet Wambacq; Maarten Kuijk; Jan Craninckx (ISSCC, 2008)

A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS. - Jonathan Borremans; Piet Wambacq; Maarten Kuijk; Geert Carchon; Stefaan Decoutere (ISSCC, 2008)

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS. - Karen Scheir; Stephane Bronckers; Jonathan Borremans; Piet Wambacq; Yves Rolain (ISSCC, 2008)

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (ISSCC, 2008)

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. - Piet Wambacq; Abdelkarim Mercha; Karen Scheir; Bob Verbruggen; Jonathan Borremans; Vincent De Heyn; Steven Thijs; Dimitri Linten; Geert Van der Plas; Bertrand Parvais; Morin Dehan; Stefaan Decoutere; et al. (ISSCC, 2008)

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. - Jonathan Borremans; Andrea Bevilacqua; Stephane Bronckers; Morin Dehan; Maarten Kuijk; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2008)

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS. - Jonathan Borremans; Piet Wambacq; Charlotte Soens; Yves Rolain; Maarten Kuijk (IEEE J. Solid State Circuits, 2008)

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS. - Karen Scheir; Stephane Bronckers; Jonathan Borremans; Piet Wambacq; Yves Rolain (IEEE J. Solid State Circuits, 2008)

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0.13-mu m CMOS. - Pieter Crombez; Jan Craninckx; Piet Wambacq; Michiel Steyaert (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Low-cost feedback-enabled LNAs in 45nm CMOS. - Jonathan Borremans; Steven Thijs; Morin Dehan; Abdelkarim Mercha; Piet Wambacq (ESSCIRC, 2009)

FinFET RF receiver building blocks operating above 10 GHz. - Domagoj Siprak; Piet Wambacq; Bertrand Parvais; Abdelkarim Mercha; Michael Fulde; Jesenka Veledar Kruger; Morin Dehan; Stefaan Decoutere (ESSCIRC, 2009)

A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS. - Jonathan Borremans; Kuba Raczkowski; Piet Wambacq (ISSCC, 2009)

50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS. - Kuba Raczkowski; Steven Thijs; Walter De Raedt; Bart Nauwelaers; Piet Wambacq (ISSCC, 2009)

A 57-to-66GHz quadrature PLL in 45nm digital CMOS. - Karen Scheir; Gerd Vandersteen; Yves Rolain; Piet Wambacq (ISSCC, 2009)

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. - Jonathan Borremans; Julien Ryckaert; Claude Desset; Maarten Kuijk; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2009)

A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA. - Jonathan Borremans; Steven Thijs; Piet Wambacq; Yves Rolain; Dimitri Linten; Maarten Kuijk (IEEE J. Solid State Circuits, 2009)

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (IEEE J. Solid State Circuits, 2009)

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes. - Dimitri Linten; Steven Thijs; Jonathan Borremans; Morin Dehan; David Trémouilles; Mirko Scholz; M. I. Natarajan; Piet Wambacq; Stefaan Decoutere; Guido Groeseneken (Microelectron. Reliab., 2009)

A 40 nm LP CMOS PLL for high-speed mm-wave communication. - Bertrand Parvais; Karen Scheir; Vojkan Vidojkovic; R. Vandebriel; Gerd Vandersteen; Charlotte Soens; Piet Wambacq (ESSCIRC, 2010)

A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS. - Piet Wambacq; Vito Giannini; Karen Scheir; Wim Van Thillo; Yves Rolain (ESSCIRC, 2010)

A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS. - Kuba Raczkowski; Walter De Raedt; Bart Nauwelaers; Piet Wambacq (ISSCC, 2010)

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (ISSCC, 2010)

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (IEEE J. Solid State Circuits, 2010)

A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. - Wagdy M. Gaber; Piet Wambacq; Jan Craninckx; Mark Ingels (ESSCIRC, 2011)

A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. - Wagdy M. Gaber; Piet Wambacq; Jan Craninckx; Mark Ingels (ESSCIRC, 2012)

A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. - Badr Malki; Takaya Yamamoto; Bob Verbruggen; Piet Wambacq; Jan Craninckx (ISSCC, 2012)

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s. - Vojkan Vidojkovic; Giovanni Mangraviti; Khaled Khalaf; Viki Szortyka; Kristof Vaesen; Wim Van Thillo; Bertrand Parvais; Mike Libois; Steven Thijs; John R. Long; Charlotte Soens; Piet Wambacq (ISSCC, 2012)

CMOS low-power transceivers for 60GHz multi Gbit/s communications. - Vojkan Vidojkovic; Viki Szortyka; Khaled Khalaf; Giovanni Mangraviti; Bertrand Parvais; Kristof Vaesen; Steven Brebels; Annachiara Spagnolo; Michael Libois; John R. Long; Kuba Raczkowski; Praveen Raghavan; et al. (CICC, 2013)

F6: Mixed-signal/RF design and modeling in next-generation CMOS. - Boris Murmann; Jafar Savoj; Piet Wambacq; Jieh-Tsorng Wu (ISSCC, 2013)

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication. - Vojkan Vidojkovic; Viki Szortyka; Khaled Khalaf; Giovanni Mangraviti; Steven Brebels; Wim Van Thillo; Kristof Vaesen; Bertrand Parvais; Vadim Issakov; Mike Libois; Michiaki Matsuo; John R. Long; et al. (ISSCC, 2013)

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). - Min Li 001; Khaled Khalaf; Chunshu Li; Vojkan Vidojkovic; Mark Ingels; André Bourdoux; Piet Wambacq; Jan Craninckx; Liesbet Van der Perre (SiPS, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. - Badr Malki; Bob Verbruggen; Piet Wambacq; Kazuaki Deguchi; Masao Iriguchi; Jan Craninckx (ESSCIRC, 2014)

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. - Nereo Markulic; Kuba Raczkowski; Piet Wambacq; Jan Craninckx (ESSCIRC, 2014)

A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C. - Alaa Medra; Vito Giannini; Davide Guermandi; Piet Wambacq (ESSCIRC, 2014)

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. - Annachiara Spagnolo; Bob Verbruggen; Stefano D'Amico; Piet Wambacq (ESSCIRC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. - Vito Giannini; Davide Guermandi; Qixian Shi; Kristof Vaesen; Bertrand Parvais; Wim Van Thillo; André Bourdoux; Charlotte Soens; Jan Craninckx; Piet Wambacq (ISSCC, 2014)

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS. - Viki Szortyka; Qixian Shi; Kuba Raczkowski; Bertrand Parvais; Maarten Kuijk; Piet Wambacq (ISSCC, 2014)

A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS. - Vito Giannini; Davide Guermandi; Qixian Shi; Alaa Medra; Wim Van Thillo; André Bourdoux; Piet Wambacq (IEEE J. Solid State Circuits, 2014)

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. - Badr Malki; Takaya Yamamoto; Bob Verbruggen; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2014)

A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS. - Annachiara Spagnolo; Bob Verbruggen; Piet Wambacq; Stefano D'Amico (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. - Bertrand Parvais; Piet Wambacq; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Ken Sawada; Kazuki Nomoto; Tetsuya Oishi; Hiroaki Ammo (A-SSCC, 2015)

Flicker noise upconversion mechanisms in K-band CMOS VCOs. - Qixian Shi; Davide Guermandi; Jan Craninckx; Piet Wambacq (A-SSCC, 2015)

A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS. - Khaled Khalaf; Vojkan Vidojkovic; John R. Long; Piet Wambacq (ESSCIRC, 2015)

A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. - Barend van Liempd; Saneaki Ariumi; Ewout Martens; Shih-Hung Chen; Piet Wambacq; Jan Craninckx (ESSCIRC, 2015)

An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. - Barend van Liempd; Benjamin P. Hershberg; Björn Debaillie; Piet Wambacq; Jan Craninckx (ESSCIRC, 2015)

A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. - Badr Malki; Bob Verbruggen; Ewout Martens; Piet Wambacq; Jan Craninckx (ESSCIRC, 2015)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

High-speed analog-to-digital converters in downscaled CMOS. - Annachiara Spagnolo; Bob Verbruggen; Stefano D'Amico; Piet Wambacq (ICICDT, 2015)

9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. - Pedro Emiliano Paro Filho; Mark Ingels; Piet Wambacq; Jan Craninckx (ISSCC, 2015)

19.7 A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS. - Davide Guermandi; Qixian Shi; Alaa Medra; Tomohiro Murata; Wim Van Thillo; André Bourdoux; Piet Wambacq; Vito Giannini (ISSCC, 2015)

F5: Advanced RF CMOS transmitter techniques. - Piet Wambacq; Stefano Pellerano; Sven Mattisson; Shouhei Kousai; Ali Afsahi; Taizo Yamawaki (ISSCC, 2015)

An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. - Pedro Emiliano Paro Filho; Mark Ingels; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2015)

Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". - Badr Malki; Takaya Yamamoto; Bob Verbruggen; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2015)

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. - Viki Szortyka; Qixian Shi; Kuba Raczkowski; Bertrand Parvais; Maarten Kuijk; Piet Wambacq (IEEE J. Solid State Circuits, 2015)

A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers. - Viki Szortyka; Kuba Raczkowski; Maarten Kuijk; Piet Wambacq (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. - Chunshu Li; Min Li 001; Khaled Khalaf; André Bourdoux; Marian Verhelst; Mark Ingels; Piet Wambacq; Jan Craninckx; Liesbet Van der Perre; Sofie Pollin (J. Signal Process. Syst., 2015)

Data Transmission at Millimeter Waves - Exploiting the 60 GHz Band on Silicon - Khaled Khalaf; Vojkan Vidojkovic; Piet Wambacq; John R. Long (Springer, 2015)

A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS. - Davide Guermandi; Qixian Shi; Andy Dewilde; Veerle Derudder; Ubaid Ahmad; Annachiara Spagnolo; André Bourdoux; Piet Wambacq; Wim Van Thillo (A-SSCC, 2016)

A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter. - Yanxiang Huang; Chunshu Li; Khaled Khalaf; André Bourdoux; Julien Verschueren; Qixian Shi; Piet Wambacq; Sofie Pollin; Wim Dehaene; Liesbet Van der Perre (A-SSCC, 2016)

13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. - Pedro Emiliano Paro Filho; Mark Ingels; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. - Benjamin P. Hershberg; Barend van Liempd; Xiaoqiang Zhang 008; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS. - Giovanni Mangraviti; Khaled Khalaf; Qixian Shi; Kristof Vaesen; Davide Guermandi; Vito Giannini; Steven Brebels; Fortunato Frazzica; André Bourdoux; Charlotte Soens; Wim Van Thillo; Piet Wambacq (ISSCC, 2016)

9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

A Fractional-n subsampling PLL based on a digital-to-time converter. - Nereo Markulic; Kuba Raczkowski; Piet Wambacq; Jan Craninckx (MIPRO, 2016)

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication. - Khaled Khalaf; Vojkan Vidojkovic; Kristof Vaesen; Michael Libois; Giovanni Mangraviti; Viki Szortyka; Chunshu Li; Bob Verbruggen; Mark Ingels; André Bourdoux; Charlotte Soens; Wim Van Thillo; et al. (IEEE J. Solid State Circuits, 2016)

A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. - Badr Malki; Bob Verbruggen; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2016)

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2016)

An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars. - Alaa Medra; Davide Guermandi; Kristof Vaesen; Steven Brebels; André Bourdoux; Wim Van Thillo; Piet Wambacq; Vito Giannini (IEEE J. Solid State Circuits, 2016)

An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS. - Oscar Elisio Mattia; Davide Guermandi; Guy Torfs; Piet Wambacq (CICC, 2017)

A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS. - Khaled Khalaf; Kristof Vaesen; Steven Brebels; Giovanni Mangraviti; Michael Libois; Charlotte Soens; Piet Wambacq (ESSCIRC, 2017)

A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. - Cheng-Hsueh Tsai; Giovanni Mangraviti; Qixian Shi; Khaled Khalaf; André Bourdoux; Piet Wambacq (ESSCIRC, 2017)

Session 17 overview: TX and RX building blocks. - Brian P. Ginsburg; Payam Heydari; Piet Wambacq (ISSCC, 2017)

Session 19 overview: Frequency generation. - Andrea Mazzanti; Xiang Gao; Piet Wambacq (ISSCC, 2017)

Session 2 overview: Power amplifiers. - Kohei Onizuka; Abbas Komijani; Piet Wambacq (ISSCC, 2017)

A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. - Davide Guermandi; Qixian Shi; Andy Dewilde; Veerle Derudder; Ubaid Ahmad; Annachiara Spagnolo; Ilja Ocket; André Bourdoux; Piet Wambacq; Jan Craninckx; Wim Van Thillo (IEEE J. Solid State Circuits, 2017)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (CICC, 2018)

Scaling CMOS beyond Si FinFET: an analog/RF perspective. - Bertrand Parvais; Geert Hellings; Marko Simicic; Pieter Weckx; Jérôme Mitard; Doyoung Jang; V. Deshpande; B. van Liempc; Anabela Veloso; A. Vandooren; Niamh Waldron; Piet Wambacq; et al. (ESSDERC, 2018)

Session 26 overview: RF techniques for communication and sensing: RF subcommittee. - Giuseppe Gramegna; Hua Wang; Piet Wambacq (ISSCC, 2018)

Session 15 overview: RF PLLs: RF subcommittee. - Jiayoon Ru; Jaehyouk Choi; Piet Wambacq (ISSCC, 2018)

Session 23 overview: LO generation: RF subcommittee. - Hyunchol Shin; Andrea Bevilacqua; Piet Wambacq (ISSCC, 2018)

A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. - Nereo Markulic; Pratap Renukaswarny; Ewout Martens; Barend van Liempd; Piet Wambacq; Jan Craninckx (VLSI Circuits, 2018)

A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS. - Khaled Khalaf; Kristof Vaesen; Steven Brebels; Giovanni Mangraviti; Michael Libois; Charlotte Soens; Wim Van Thillo; Piet Wambacq (IEEE J. Solid State Circuits, 2018)

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. - Lin-Kun Wu; David San Segundo Bello; Philippe Coppejans; Jan Craninckx; Andreas Süss; Maarten Rosmeulen; Piet Wambacq; Jonathan Borremans (Sensors, 2018)

Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). - Aritra Banerjee; Kristof Vaesen; Akshay Visweswaran; Khaled Khalaf; Qixian Shi; Steven Brebels; Davide Guermandi; Cheng-Hsueh Tsai; Johan Nguyen; Alaa Medra; Yao Liu; Giovanni Mangraviti; et al. (CICC, 2019)

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. - Cheng-Hsueh Tsai; Federico Pepe; Giovanni Mangraviti; Zhiwei Zong; Jan Craninckx; Piet Wambacq (ESSCIRC, 2019)

A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE. - Akshay Visweswaran; Bastien Vignon; Xinyan Tang; Steven Brebels; Björn Debaillie; Piet Wambacq (ESSCIRC, 2019)

A 145GHz FMCW-Radar Transceiver in 28nm CMOS. - Akshay Visweswaran; Kristof Vaesen; Siddhartha Sinha; Ilja Ocket; Miguel Glassee; Claude Desset; André Bourdoux; Piet Wambacq (ISSCC, 2019)

Systematic Design of On-Chip Matching Networks for D-band Circuits. - Johan Nguyen; Xinyan Tang; Khaled Khalaf; Björn Debaillie; Piet Wambacq (NEWCAS, 2019)

Design of A D-band Transformer-Based Neutralized Class-AB Power Amplifier in Silicon Technologies. - Xinyan Tang; Alaaeldien Medra; Johan Nguyen; Khaled Khalaf; Björn Debaillie; Piet Wambacq (NEWCAS, 2019)

Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. - Dongyang Yan; Mark Ingels; Giovanni Mangraviti; Yao Liu; Bertrand Parvais; Niamh Waldron; Nadine Collaert; Piet Wambacq (NEWCAS, 2019)

A 22-29 GHz Voltage-Biased LC-VCO with Suppressed Flicker Noise over Tuning Range in 22nm FD-SOI. - Zhiwei Zong; Giovanni Mangraviti; Piet Wambacq (NEWCAS, 2019)

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. - Nereo Markulic; Pratap Tumkur Renukaswamy; Ewout Martens; Barend van Liempd; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

Multi-User Hybrid MIMO at 60 GHz Using 16-Antenna Transmitters. - Steve Blandino; Giovanni Mangraviti; Claude Desset; André Bourdoux; Piet Wambacq; Sofie Pollin (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI. - Zhiwei Zong; Xinyan Tang; Johan Nguyen; Khaled Khalaf; Giovanni Mangraviti; Yao Liu; Piet Wambacq (CICC, 2020)

A 1st Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC. - Toshio Yasue; Fortunato Frazzica; Annachiara Spagnolo; David San Segundo Bello; Maarten De Bock; Piet Wambacq; Jan Craninckx (IEEE SENSORS, 2020)

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Sehoon Park; Anirudh Kankuppe; Qixian Shi; Piet Wambacq; Jan Craninckx (ISSCC, 2020)

A flexible power model for mm-wave and THz high-throughput communication systems. - Claude Desset; Piet Wambacq; Yang Zhang 081; Mark Ingels; André Bourdoux (PIMRC, 2020)

A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique. - Dae-Woong Park; Dzuhri Radityo Utomo; Jong-Phil Hong; Kristof Vaesen; Piet Wambacq; Sang-Gug Lee 001 (VLSI Circuits, 2020)

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2020)

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. - Cheng-Hsueh Tsai; Zhiwei Zong; Federico Pepe; Giovanni Mangraviti; Jan Craninckx; Piet Wambacq (IEEE J. Solid State Circuits, 2020)

Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies. - Xinyan Tang; Johan Nguyen; Alaaeldien Medra; Khaled Khalaf; Akshay Visweswaran; Björn Debaillie; Piet Wambacq (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Low 1/f3 Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI. - Zhiwei Zong; Giovanni Mangraviti; Piet Wambacq (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. - Alican Çaglar; Steven Van Winckel; Steven Brebels; Piet Wambacq; Jan Craninckx (A-SSCC, 2021)

A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. - Sriram Balamurali; Giovanni Mangraviti; Cheng-Hsueh Tsai; Piet Wambacq; Jan Craninckx (ESSCIRC, 2021)

A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. - Anirudh Kankuppe; Sehoon Park; Kristof Vaesen; Dae-Woong Park; Barend van Liempd; Piet Wambacq; Jan Craninckx (ESSCIRC, 2021)

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ESSCIRC, 2021)

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (ISCAS, 2021)

26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS. - Yang Zhang 081; Giovanni Mangraviti; Johan Nguyen; Zhiwei Zong; Piet Wambacq (ISSCC, 2021)

A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization. - Akshay Visweswaran; Kristof Vaesen; Miguel Glassee; Anirudh Kankuppe; Siddhartha Sinha; Claude Desset; Thomas Gielen; André Bourdoux; Piet Wambacq (IEEE J. Solid State Circuits, 2021)

A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS. - Yang Zhang 081; Giovanni Mangraviti; Johan Nguyen; Zhiwei Zong; Kamil Yavuz Kapusuz; Sam Lemey; Hendrik Rogier; Giuseppe Gramegna; Piet Wambacq (IEEE J. Solid State Circuits, 2021)

A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. - Steven Van Winckel; Alican Çaglar; Benjamin Gys; Steven Brebels; Anton Potocnik; Bertrand Parvais; Piet Wambacq; Jan Craninckx (ESSCIRC, 2022)

III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance. - Abhitosh Vais; Sachin Yadav 001; Yves Mols; Bjorn Vermeersch; Komal Vondkar Kodandarama; Marina Baryshnikova; G. Mannaert; R. Alcotte; Geert Boccardi; Piet Wambacq; Bertrand Parvais; R. Langer; et al. (ESSDERC, 2022)

Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. - Sriram Balamurali; Giovanni Mangraviti; Cheng-Hsueh Tsai; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. - Anirudh Kankuppe; Sehoon Park; Kristof Vaesen; Dae-Woong Park; Barend van Liempd; Siddhartha Sinha; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. - Sehoon Park; Dae-Woong Park; Kristof Vaesen; Anirudh Kankuppe; Siddhartha Sinha; Barend van Liempd; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS. - Xinyan Tang; Johan Nguyen; Giovanni Mangraviti; Zhiwei Zong; Piet Wambacq (IEEE J. Solid State Circuits, 2022)

A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications. - Dongyang Yan; Yang Zhang 081; Dries Peumans; Mark Ingels; Piet Wambacq (BCICTS, 2023)

A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI. - Sriram Balamurali; Giovanni Mangraviti; Zhiwei Zhong; Piet Wambacq; Jan Craninckx (ESSCIRC, 2023)

A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Piet Wambacq; Jan Craninckx (ESSCIRC, 2023)

A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-End in 0.15μm GaN-on-SiC Technology. - Dongyang Yan; Sehoon Park; Yang Zhang 081; Mark Ingels; Piet Wambacq (ESSCIRC, 2023)

A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs. - Rana Y. El Kashlan; Hao Yu; Ahmad Khaled; Sachin Yadav 001; Uthayasankaran Peralagu; AliReza Alian; Nadine Collaert; Piet Wambacq; Bertrand Parvais (ESSDERC, 2023)

A 16GHz, $41 text{kHz}_{ text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. - Pratap Tumkur Renukaswamy; Kristof Vaesen; Nereo Markulic; Veerle Derudder; Dae-Woong Park; Piet Wambacq; Jan Craninckx (ISSCC, 2023)

The Promise of 2-D Materials for Scaled Digital and Analog Applications. - Devin Verreck; Piet Wambacq; Maarten Van De Put; Zubair Ahmed; Quentin Smets; Aryan Afzalian; Rutger Duflou; Xiangyu Wu; Gioele Mirabelli; Rongmei Chen; Inge Asselberghs; Gouri Sankar Kar (ISSCC, 2023)

Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design. - Piet Wambacq (ISSCC, 2023)

A 0.13μm GaAs HEMT Reconfigurable Balance-to-Doherty Stacked Power Amplifier for 5G mm-wave Applications. - Dongyang Yan; Yang Zhang 081; Mark Ingels; Piet Wambacq (PRIME, 2023)

Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout. - Alican Çaglar; Steven Van Winckel; Steven Brebels; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2023)

Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS. - Johan Nguyen; Khaled Khalaf; Xinyan Tang; Steven Brebels; Kristof Vaesen; Mithlesh Shrivas; Piet Wambacq (IEEE J. Solid State Circuits, 2023)

A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psat and 24.3 % PAE in a 250-nm InP HBT Technology. - Arno Hemelhof; Sehoon Park; Yang Zhang 081; Mark Ingels; Giuseppe Gramegna; Kristof Vaesen; Dongyang Yan; Piet Wambacq (BCICTS, 2024)

Resource-Efficient Gesture Recognition Using Low-Resolution Thermal Camera via Spiking Neural Networks and Sparse Segmentation. - Ali Safa; Wout Mommen; Piet Wambacq; Lars Keuninckx (FG, 2024)

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. - S.-H. Lin; Marko Simicic; N. Pantano; S.-H. Chen; Geert Van der Plas; Eric Beyne; Piet Wambacq (VLSI Technology and Circuits, 2024)

Photonics-enabled Code-Division Multiplexing FMCW Distributed Radar. - Chang-Shao Shen; Nishant Singh; Anirudh Kankuppe; Kristof Vaesen; Piet Wambacq; Guy Torfs (OFC, 2025)

A Method for Optimizing Connections in Differentiable Logic Gate Networks. - Wout Mommen; Lars Keuninckx; Matthias Hartmann; Piet Wambacq (CoRR, 2025)