Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Memories for NTC. - Tobias Gemmeke; Mohamed M. Sabry; Jan Stuijt; Pieter Schuddinck; Praveen Raghavan; Francky Catthoor (Near Threshold Computing, 2016)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Dmitry Yakimets; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ESSDERC, 2017)

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ICICDT, 2017)

Design enablement of CFET devices for sub-2nm CMOS nodes. - Odysseas Zografos; Bilal Chehab; Pieter Schuddinck; Gioele Mirabelli; Naveen Kakarla; Yang Xiang; Pieter Weckx; Julien Ryckaert (DATE, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. - Pieter Schuddinck; Fabian M. Bufler; Yang Xiang; Anita Farokhnejad; Gioele Mirabelli; Anne Vandooren; Bilal Chehab; A. Gupta; César Roda Neve; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2022)

Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. - Bjorn Vermeersch; Erik Bury; Yang Xiang; Pieter Schuddinck; Krishna K. Bhuwalka; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2022)

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. - S. Yang; Pieter Schuddinck; Marie Garcia Bardon; Yang Xiang; Anabela Veloso; B. T. Chan; Gioele Mirabelli; Gaspard Hiblot; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2023)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)