ECL-CMOS and CMOS-ECL interface in 1.2- mu m CMOS for 150-MHz digital ECL data transmission systems. - Michel S. J. Steyaert; Wout Bijker; Pieter Vorenkamp; Jan Sevenhans (IEEE J. Solid State Circuits, 1991)

Fully bipolar, 120-Msample/s 10-b track-and-hold circuit. - Pieter Vorenkamp; Johan P. M. Verdaasdonk (IEEE J. Solid State Circuits, 1992)

A 12-b, 60-MSample/s cascaded folding and interpolating ADC. - Pieter Vorenkamp; Raf Roovers (IEEE J. Solid State Circuits, 1997)

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0. - Francesco Gatta; Ray Gomez; Young Shin; Takayuki Hayashi; Hanli Zou; James Y. C. Chang; Leonard Dauphinee; Jianhong Xiao; Dave S.-H. Chang; Tai-Hong Chih; Massimo Brandolini; Dongsoo Koh; et al. (ISSCC, 2009)

An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0. - Francesco Gatta; Ray Gomez; Young J. Shin; Takayuki Hayashi; Hanli Zou; James Y. C. Chang; Leonard Dauphinee; Jianhong Xiao; Dave S.-H. Chang; Tai-Hong Chih; Massimo Brandolini; Dongsoo Koh; et al. (IEEE J. Solid State Circuits, 2009)

A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor. - David Garrett; Youn Sung Park; Seongjong Kim; Jay Sharma; Wenbin Huang; Majid Shaghaghi; Vinay Parthasarathy; Stephen Gibellini; Stephen Bailey; Mallik Moturi; Pieter Vorenkamp; Kurt Busch; et al. (ISSCC, 2023)