The U-PHOS experience within the ESA student REXUS/BEXUS programme: A real space hands-on opportunity. - Pietro Nannipieri; Martina Anichini; Lorenzo Barsocchi; Giulia Becatti; Luca Buoni; Andrea Catarsi; Federico Celi; Paolo Di Giorgio; Paolo Fattibene; Eugenio Ferrato; Pietro Guardati; Edoardo Mancini; et al. (EDUCON, 2017)

A PXI Based Implementation of a TLK2711 Equivalent Interface. - Pietro Nannipieri; Luca Dello Sterpaio; Antonino Marino; Luca Fanucci (ApplePies, 2018)

A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE. - Pietro Nannipieri; Gianmarco Dinelli; Daniele Davalle; Luca Fanucci (PRIME, 2018)

A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution. - Pietro Nannipieri; Daniele Davalle; Luca Fanucci (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus. - Gianmarco Dinelli; Gabriele Meoni; Pietro Nannipieri; Luca Dello Sterpaio; Antonino Marino; Luca Fanucci (ApplePies, 2019)

Design of a SpaceFibre High-Speed Satellite Interface ASIC. - Pietro Nannipieri; Gianmarco Dinelli; Luca Dello Sterpaio; Antonino Marino; Luca Fanucci (ApplePies, 2019)

AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA. - Luca Dello Sterpaio; Antonino Marino; Pietro Nannipieri; Gianmarco Dinelli; Luca Fanucci (ApplePies, 2019)

Exploiting LabViewFpga Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards. - Luca Dello Sterpaio; Antonino Marino; Pietro Nannipieri; Luca Fanucci (SMACD, 2019)

VHDL Design of a SpaceFibre Routing Switch. - Alessandro Leoni; Pietro Nannipieri; Luca Fanucci (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case. - Pietro Nannipieri; Gianmarco Dinelli; Luca Fanucci (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard. - Luca Dello Sterpaio; Antonino Marino; Pietro Nannipieri; Gianmarco Dinelli; Daniele Davalle; Luca Fanucci (Sensors, 2019)

Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation. - Pietro Nannipieri; Daniele Davalle; Stefano Nencioni; Paolo Lombardi; Luca Fanucci (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019)

CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes. - Pietro Nannipieri; Luca Baldanzi; Luca Crocetti; Stefano Di Matteo; Francesco Falaschi; Luca Fanucci; Sergio Saponara (ApplePies, 2021)

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. - Luca Zulberti; Pietro Nannipieri; Luca Fanucci (DTIS, 2021)

A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. - Pietro Nannipieri; Stefano Di Matteo; Luca Zulberti; Francesco Albicocchi; Sergio Saponara; Luca Fanucci (IEEE Access, 2021)

SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative. - Pietro Nannipieri; Matteo Bertolucci; Luca Baldanzi; Luca Crocetti; Stefano Di Matteo; Francesco Falaschi; Luca Fanucci; Sergio Saponara (Microprocess. Microsystems, 2021)

Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators. - Luca Zulberti; Matteo Monopoli; Pietro Nannipieri; Luca Fanucci (PRIME, 2022)

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source. - Luca Crocetti; Stefano Di Matteo; Pietro Nannipieri; Luca Fanucci; Sergio Saponara (Entropy, 2022)

VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. - Pietro Nannipieri; Stefano Di Matteo; Luca Baldanzi; Luca Crocetti; Luca Zulberti; Sergio Saponara; Luca Fanucci (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A PUF-Based Secure Boot for RISC-V Architectures. - Stefano Di Matteo; Luca Zulberti; Federico Cosimo Lapenna; Pietro Nannipieri; Luca Crocetti; Luca Fanucci; Sergio Saponara (ApplePies, 2023)

Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. - Pietro Nannipieri; Stefano Di Matteo; Luca Crocetti; Luca Zulberti; Luca Fanucci; Sergio Saponara (ApplePies, 2023)

Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip. - Matteo Monopoli; Luca Zulberti; Giovanni Todaro; Pietro Nannipieri; Luca Fanucci (PRIME, 2023)

Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry. - Giovanni Quintarelli; Matteo Bertolucci; Pietro Nannipieri (IEEE Access, 2023)

SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario. - Roberto Ciardi; Simone Vagaggini; Antonino Marino; Pietro Nannipieri; Luca Fanucci (Sensors, 2023)

Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine. - Gabriela Mystkowska; Luca Zulberti; Matteo Monopoli; Pietro Nannipieri; Luca Fanucci (DSD, 2024)

SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems. - Luca Zulberti; Andrea Monorchio; Matteo Monopoli; Gabriela Mystkowska; Pietro Nannipieri; Luca Fanucci (DSD, 2024)

Enhancing a Soft GPU IP Reliability Against SEUs in Space: Modelling Approach and Criticality Analysis on a Radiation-Tolerant FPGA. - Matteo Monopoli; Matteo Biondi; Giovanni Todaro; Pietro Nannipieri; Silvia Moranti; Cinzia Bernardeschi; Luca Fanucci (ICSRS, 2024)

Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload. - Pietro Nannipieri; Giacomo Bartolacci; Matteo Bertolucci; Luca Fanucci (IEEE Access, 2024)

Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems. - Simone Vagaggini; Daniele Davalle; Pietro Nannipieri; Luca Fanucci (IEEE Access, 2024)

RADSAFiE: A Netlist-Level Fault Injection User Interface Application for FPGA-Based Digital Systems. - Matteo Monopoli; Matteo Biondi; Pietro Nannipieri; Silvia Moranti; Luca Fanucci (IEEE Access, 2025)

FPG-AI RNN: A Technology-Agnostic Framework for the Automatic Acceleration of LSTM/GRU-Based Models on FPGAs. - Tommaso Pacini; Pietro Nannipieri; Silvia Moranti; Luca Fanucci (IEEE Access, 2025)

Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform. - Luca Zulberti; Matteo Monopoli; Pietro Nannipieri; Silvia Moranti; Geert Thys; Luca Fanucci (Microprocess. Microsystems, 2025)

Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative. - Pietro Nannipieri; Luca Crocetti; Stefano Di Matteo; Luca Fanucci; Sergio Saponara (IEEE Trans. Computers, 2025)