A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (CICC, 2024)

34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS. - Simone Mattia Dartizio; Giacomo Castoro; Stefano Gallucci; Michele Rossoni; Riccardo Moleri; Francesco Tesolin; Pietro Salvi; Saleh Karman; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning. - Stefano Gallucci; Francesco Tesolin; Pietro Salvi; Daniele Lodi Rizzini; Riccardo Moleri; Francesco Buccoleri; Michele Rossoni; Giacomo Castoro; Simone Mattia Dartizio; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2025)