A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle. - Pil-Ho Lee; Hyun Bae Lee; Young-Chan Jang (IEICE Trans. Electron., 2014)

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. - Pil-Ho Lee; Yu-Jeong Hwang; Han-Yeol Lee; Hyun Bae Lee; Young-Chan Jang (IEICE Trans. Electron., 2016)

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators. - Sang-Min Park; Yeon-Ho Jeong; Yu-Jeong Hwang; Pil-Ho Lee; Yeong-Woong Kim; Jisu Son; Han-Yeol Lee; Young-Chan Jang (IEICE Trans. Electron., 2016)

0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch. - Seung-Hun Shin; Pil-Ho Lee; Jin-Woo Park; Yu-Jeong Hwang; Young-Chan Jang (ISCAS, 2017)

A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver. - Jin-Wook Han; Pil-Ho Lee; Yeong-Woong Kim; Sang-Dong Kim; Jin-Woo Park; Young-Chan Jang (ISOCC, 2017)

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display. - Ho-Seong Kim; Pil-Ho Lee; Jin-Wook Han; Seung-Hun Shin; Seung-Wuk Baek; Doo-Ill Park; Yongkyu Seo; Young-Chan Jang (IEICE Trans. Electron., 2017)

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2. - Pil-Ho Lee; Han-Yeol Lee; Yeong-Woong Kim; Han-Young Hong; Young-Chan Jang (IEEE Trans. Consumer Electron., 2017)

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. - Pil-Ho Lee; Han-Yeol Lee; Hyun Bae Lee; Young-Chan Jang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip. - Pil-Ho Lee; Young-Chan Jang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface. - Pil-Ho Lee; Young-Chan Jang (IEEE Trans. Consumer Electron., 2019)

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization. - Pil-Ho Lee; Young-Chan Jang (IEEE Trans. Circuits Syst., 2020)

A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. - Junghoon Jin; Seungjun Kim; Sunguk Choi; Pil-Ho Lee; Sang-jae Rhee; Ki-hwan Choi; Jongsun Kim (ISOCC, 2021)

A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC. - Chaeyoung Jang; Pil-Ho Lee; Sang-jae Rhee; Ki-hwan Choi; Jongsun Kim (ICEIC, 2022)

Strategic design and simulation of interfaces for enhanced joint performance in metal-polymer hybrid structures. - Seong Je Park; Joon Phil Choi; Pil-Ho Lee; Seung Ki Moon (J. Comput. Des. Eng., 2025)