Evaluation of Three Interconnection Networks for CMOS VLSI Implementation. - Pinaki Mazumder (ICPP, 1986)

Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. - Pinaki Mazumder; Janak H. Patel; W. Kent Fuchs (DAC, 1987)

Planar decomposition for quadtree data structure. - Pinaki Mazumder (Comput. Vis. Graph. Image Process., 1987)

Evaluation of On-Chip Static Interconnection Networks. - Pinaki Mazumder (IEEE Trans. Computers, 1987)

An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory. - Pinaki Mazumder (ITC, 1988)

Methodologies for testing embedded content addressable memories. - Pinaki Mazumder; Janak H. Patel; W. Kent Fuchs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Testing and Fault-Tolerance Aspects of High-Density VLSI Memory - Pinaki Mazumder (1988)

Parallel testing of parametric faults in a three-dimensional dynamic random-access memory. - Pinaki Mazumder (IEEE J. Solid State Circuits, 1988)

Neural computing for built-in self-repair of embedded memory arrays. - Pinaki Mazumder; Jih-Shyr Yih (FTCS, 1989)

HAM-a hardware accelerator for multi-layer wire routing. - Raja Venkateswaran; Pinaki Mazumder (ICCAD, 1989)

Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. - Pinaki Mazumder; Janak H. Patel (IEEE Trans. Computers, 1989)

GASP: a Genetic Algorithm for Standard cell Placement. - Khushro Shahookar; Pinaki Mazumder (EURO-DAC, 1990)

A Parallel Karmarkar Algorithm on Orthogonal Tree Networks. - R. B. Panwar; Pinaki Mazumder (ICPP (3), 1990)

A novel built-in self-repair approach to VLSI memory yield enhancement. - Pinaki Mazumder; Jih-Shyr Yih (ITC, 1990)

A genetic approach to standard cell placement using meta-genetic parameter optimization. - Khushro Shahookar; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A hexagonal array machine for multilayer wire routing. - Raja Venkateswaran; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A neural network design for circuit partitioning. - Jih-Shyr Yih; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A reconfigurable parallel signature analyzer for concurrent error correction in DRAM. - Pinaki Mazumder; Janak H. Patel; Jacob A. Abraham (IEEE J. Solid State Circuits, 1990)

Fault Modeling and Testing of GaAs Static Random Access Memories. - Sundarar Mohan; Pinaki Mazumder (ITC, 1991)

VLSI Cell Placement Techniques. - Khushro Shahookar; Pinaki Mazumder (ACM Comput. Surv., 1991)

Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome. - Heming Chan; Pinaki Mazumder; Khushro Shahookar (Integr., 1991)

Circuit behavior modeling and compact testing performance evaluation. - Jih-Shyr Yih; Pinaki Mazumder (IEEE J. Solid State Circuits, 1991)

An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays. - Pinaki Mazumder (ITC, 1992)

An efficient design of embedded memories and their testability analysis using Markov chains. - Pinaki Mazumder; Janak H. Patel (J. Electron. Test., 1992)

Restructuring WSI hexagonal processor arrays. - Raja Venkateswaran; Pinaki Mazumder; K. G. Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors. - Pinaki Mazumder (IEEE J. Solid State Circuits, 1992)

Genetic Beam Search for Gate Matrix Layout. - Khushro Shahookar; W. Khamisani; Pinaki Mazumder; Sudhakar M. Reddy (VLSI Design, 1993)

Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories. - Pinaki Mazumder; John P. Hayes (IEEE Des. Test Comput., 1993)

Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit. - Pinaki Mazumder (IEEE Trans. Computers, 1993)

A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. - Pinaki Mazumder; Jih-Shyr Yih (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Restructuring of square processor arrays by built-in self-repair circuit. - Pinaki Mazumder; Jih-Shyr Yih (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Wolverines: standard cell placement on a network of workstations. - Sundarar Mohan; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors. - Sundarar Mohan; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Coprocessor design for multilayer surface-mounted PCB routing. - Raja Venkateswaran; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 1993)

A Genetic Algorithm for the Steiner Problem in a Graph. - Henrik Esbensen; Pinaki Mazumder (EDAC-ETC-EUROASIC, 1994)

A Systolic Architecture for High Speed Hypergraph Partitioning Using a Genetic Algorithm. - Heming Chan; Pinaki Mazumder (Evo Workshops, 1994)

SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement. - Henrik Esbensen; Pinaki Mazumder (VLSI Design, 1994)

Technology and layout-related testing of static random-access memories. - Kanad Chakraborty; Pinaki Mazumder (J. Electron. Test., 1994)

Guest editor's introduction. - Pinaki Mazumder (J. Electron. Test., 1994)

A survey of DA techniques for PLD and FPGA based systems. - Raja Venkateswaran; Pinaki Mazumder (Integr., 1994)

Genetic multiway partitioning. - Khushro Shahookar; Pinaki Mazumder (VLSI Design, 1995)

Device and circuit simulation of quantum electronic devices. - Sundarar Mohan; Jian Ping Sun; Pinaki Mazumder; George I. Haddad (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. - Kanad Chakraborty; Pinaki Mazumder (ICCAD, 1996)

A high-speed 32-bit parallel correlator for spread spectrum communication. - Shriram Kulkarni; Pinaki Mazumder; George I. Haddad (VLSI Design, 1996)

Compact multiple-valued multiplexers using negative differential resistance devices. - H. L. Chan; Sundarar Mohan; Pinaki Mazumder; George I. Haddad (IEEE J. Solid State Circuits, 1996)

Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays. - Michael D. Smith 005; Pinaki Mazumder (IEEE Trans. Computers, 1996)

Compact Signed-Digit Adder Using Multiple-Valued Logic. - Alejandro F. González; Pinaki Mazumder (ARVLSI, 1997)

A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. - Kanad Chakraborty; Pinaki Mazumder (ED&TC, 1997)

A Silicon Compiler for Fault-Tolerant ROMs. - Anurag Gupta; Kanad Chakraborty; Pinaki Mazumder (DFT, 1998)

Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. - Mayukh Bhattacharya; Pinaki Mazumder (Great Lakes Symposium on VLSI, 1998)

Circuit Design using Resonant Tunneling Diodes. - Pinaki Mazumder; Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González (VLSI Design, 1998)

Analysis of Failures in Deep Submicron SRAM Cells. - Pinaki Mazumder (VTS, 1998)

FTROM: A Silicon Compiler for Fault-tolerant ROMs. - Anurag Gupta; Kanad Chakraborty; Pinaki Mazumder (Integr., 1998)

Digital circuit applications of resonant tunneling devices. - Pinaki Mazumder; Shriram Kulkarni; Mayukh Bhattacharya; Jian Ping Sun; George I. Haddad (Proc. IEEE, 1998)

Resonant tunneling diodes: models and properties. - Jian Ping Sun; George I. Haddad; Pinaki Mazumder; Joel N. Schulman (Proc. IEEE, 1998)

Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices. - Alejandro F. González; Pinaki Mazumder (IEEE Trans. Computers, 1998)

Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems. - Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A Physical Design Tool for Built-in Self-Repairable Static RAMs. - Kanad Chakraborty; Anurag Gupta; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (DATE, 1999)

Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications. - Patrick Fay; Gary H. Bernstein; David H. Chow; Joel N. Schulman; Pinaki Mazumder; William Williamson III; Barry K. Gilbert (Great Lakes Symposium on VLSI, 1999)

Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. - Tetsuya Uemura; Pinaki Mazumder (Great Lakes Symposium on VLSI, 1999)

Special Issue On Quantum Devices And Their Applications. - Alan C. Seabaugh; Pinaki Mazumder (Proc. IEEE, 1999)

A prototyping technique for large-scale RTD-CMOS circuits. - Mayukh Bhattacharya; Shriram Kulkarni; Alejandro F. González; Pinaki Mazumder (ISCAS, 2000)

Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (ISMVL, 2000)

Convergence Issues in Resonant Tunneling Diode Circuit Simulation. - Mayukh Bhattacharya; Pinaki Mazumder (VLSI Design, 2000)

New March Tests for Multiport RAM Devices. - Kanad Chakraborty; Pinaki Mazumder (J. Electron. Test., 2000)

Redundant arithmetic, algorithms and implementations. - Alejandro F. González; Pinaki Mazumder (Integr., 2000)

Efficient and passive modeling of transmission lines by using differential quadrature method. - Qinwei Xu; Pinaki Mazumder (DATE, 2001)

A 250-MHz, 32-bit quantum MOS correlator prototype. - Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González; Pinaki Mazumder (ICECS, 2001)

A dual-rail static edge-triggered latch. - Li Ding 002; Pinaki Mazumder; N. Srinivas (ISCAS (2), 2001)

Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. - Mayukh Bhattacharya; Pinaki Mazumder; Ronald J. Lomax (VLSI Design, 2001)

Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. - Qinwei Xu; Pinaki Mazumder; Mayukh Bhattacharya (VLSI Design, 2001)

Transmission Line Modeling by Modified Method of Characteristics. - Qinwei Xu; Pinaki Mazumder; Zheng-Fan Li (VLSI Design, 2001)

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (IEEE J. Solid State Circuits, 2001)

Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. - Mayukh Bhattacharya; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A physical design tool for built-in self-repairable RAMs. - Kanad Chakraborty; Shriram Kulkarni; Mayukh Bhattacharya; Pinaki Mazumder; Anurag Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Optimal Transistor Tapering for High-Speed CMOS Circuits. - Li Ding 002; Pinaki Mazumder (DATE, 2002)

Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling. - Li Ding 002; Pinaki Mazumder (DATE, 2002)

Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects. - Qinwei Xu; Pinaki Mazumder (DATE, 2002)

Novel interconnect modeling by using high-order compact finite difference methods. - Qinwei Xu; Pinaki Mazumder (ACM Great Lakes Symposium on VLSI, 2002)

Efficient crosstalk noise modeling using aggressor and tree reductions. - Li Ding 002; David T. Blaauw; Pinaki Mazumder (ICCAD, 2002)

Modified long channel model for analytical study of DSM circuits. - Li Ding 002; Pinaki Mazumder (ISCAS (5), 2002)

Crosstalk noise estimation using effective coupling capacitance. - Li Ding 002; Pinaki Mazumder; David T. Blaauw (ISCAS (5), 2002)

Rise time analysis of MOBILE circuit. - Tetsuya Uemura; Pinaki Mazumder (ISCAS (5), 2002)

Novel macromodeling for on-chip RC/RLC interconnects. - Qinwei Xu; Pinaki Mazumder; Li Ding 002 (ISCAS (4), 2002)

Rational ABCD Modeling of High-Speed Interconnects. - Qinwei Xu; Pinaki Mazumder (ASP-DAC/VLSI Design, 2002)

Efficient Macromodeling for On-Chip Interconnects. - Qinwei Xu; Pinaki Mazumder (ASP-DAC/VLSI Design, 2002)

Modeling Noise Transfer Characteristic of Dynamic Logic Gates. - Li Ding 002; Pinaki Mazumder (DATE, 2003)

Subgridding method for speeding up FD-TLM circuit simulation. - Baohua Wang; Pinaki Mazumder (ISCAS (3), 2003)

Efficient interconnect modeling by Finite Difference Quadrature methods. - Qinwei Xu; Pinaki Mazumder (ISCAS (4), 2003)

Performance modeling of resonant tunneling based RAMs. - Hui Zhang; Pinaki Mazumder; Li Ding 002; Kyounghoon Yang (ISCAS (4), 2003)

The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. - Li Ding 002; Pinaki Mazumder (VLSI Design, 2003)

Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. - Alejandro F. González; Pinaki Mazumder (VLSI Design, 2003)

Accurate crosstalk noise modeling for early signal integrity analysis. - Li Ding 002; David T. Blaauw; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Simultaneous switching noise analysis using application specific device modeling. - Li Ding 002; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods. - Qinwei Xu; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A novel technique to improve noise immunity of CMOS dynamic logic circuits. - Li Ding 002; Pinaki Mazumder (DAC, 2004)

Modeling of transmission lines with EM wave coupling by the finite difference quadrature method. - Qinwei Xu; Pinaki Mazumder (ACM Great Lakes Symposium on VLSI, 2004)

On the implementation of RTD based CNNs. - Sing-Rong Li; Pinaki Mazumder; Leon O. Chua (ISCAS (3), 2004)

Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials. - Baohua Wang; Pinaki Mazumder (ISCAS (2), 2004)

Resonant tunnelling diode based QMOS edge triggered flip-flop design. - Hui Zhang; Pinaki Mazumder; Kyounghoon Yang (ISCAS (3), 2004)

On optimality of adiabatic switching in MOS energy-recovery circuit. - Baohua Wang; Pinaki Mazumder (ISLPED, 2004)

Dynamic Noise Margin: Definitions and Model. - Li Ding 002; Pinaki Mazumder (VLSI Design, 2004)

On circuit techniques to improve noise immunity of CMOS dynamic logic. - Li Ding 002; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 2004)

EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation. - Baohua Wang; Pinaki Mazumder (DATE, 2005)

New logic circuits consisting of quantum dots and CMOS. - Woo Hyung Lee; Pinaki Mazumder (ECCTD, 2005)

On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]. - Sing-Rong Li; Pinaki Mazumder; Kyounghoon Yang (ISCAS (3), 2005)

Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models. - Baohua Wang; Pinaki Mazumder (ISCAS (3), 2005)

Design of a new sense amplifier flip-flop with improved power-delay-product. - Hui Zhang; Pinaki Mazumder (ISCAS (2), 2005)

Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion. - Baohua Wang; Pinaki Mazumder (VLSI Design, 2005)

Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder. - Woo Hyung Lee; Pinaki Mazumder (ASAP, 2006)

Optimization of circuit trajectories: an auxiliary network approach. - Baohua Wang; Pinaki Mazumder (ASP-DAC, 2006)

A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function. - Baohua Wang; Pinaki Mazumder (DATE, 2006)

Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach. - Baohua Wang; Pinaki Mazumder (VLSI Design, 2006)

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. - Baohua Wang; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Efficient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method. - Qinwei Xu; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 2007)

An accurate interconnect thermal model using equivalent transmission line circuit. - Baohua Wang; Pinaki Mazumder (DATE, 2009)

Disruptive technologies and neurally-inspired architectures. - Pinaki Mazumder (ACM Great Lakes Symposium on VLSI, 2009)

Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing. - Pinaki Mazumder; Sing-Rong Li; Idongesit E. Ebong (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Threshold Read Method for Multi-bit Memristive Crossbar Memory. - Yalcin Yilmaz; Pinaki Mazumder (ISED, 2011)

Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications. - Alfredo Benso; Yiorgos Makris; Pinaki Mazumder (IEEE Trans. Computers, 2011)

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. - Kwen-Siong Chong; Joseph S. Chang; Idongesit E. Ebong; Yalcin Yilmaz; Pinaki Mazumder (ISED, 2012)

Memristor-based RRAM with applications. - Shukai Duan 001; Xiaofang Hu; Lidan Wang 001; Chuandong Li 001; Pinaki Mazumder (Sci. China Inf. Sci., 2012)

CMOS and Memristor-Based Neural Network Design for Position Detection. - Idongesit E. Ebong; Pinaki Mazumder (Proc. IEEE, 2012)

Memristors: Devices, Models, and Applications [Scanning the Issue]. - Pinaki Mazumder; Sung-Mo Kang; Rainer Waser (Proc. IEEE, 2012)

A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. - Jaeyoung Kim; Kwen-Siong Chong; Joseph Sylvester Chang; Pinaki Mazumder (ACM Great Lakes Symposium on VLSI, 2013)

Color image processing with multi-peak resonant tunneling diodes. - Woo Hyung Lee; Pinaki Mazumder (ACM J. Emerg. Technol. Comput. Syst., 2013)

Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets. - Yalcin Yilmaz; Pinaki Mazumder (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A low-power reconfigurable CMOS power amplifier for wireless sensor network applications. - Nan Zheng; Jaeyoung Kim; Pinaki Mazumder (ISCAS, 2014)

Memristor-Based Cellular Nonlinear/Neural Network: Design, Analysis, and Applications. - Shukai Duan 001; Xiaofang Hu; Zhekang Dong; Lidan Wang 001; Pinaki Mazumder (IEEE Trans. Neural Networks Learn. Syst., 2015)

Digital implementation of a virtual insect trained by spike-timing dependent plasticity. - Pinaki Mazumder; D. Hu; Idongesit E. Ebong; Xu Zhang 001; Z. Xu; Silvia Ferrari (Integr., 2016)

A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS. - Jaeyoung Kim; Pinaki Mazumder (Integr., 2017)

Hardware-Friendly Actor-Critic Reinforcement Learning Through Modulation of Spike-Timing-Dependent Plasticity. - Nan Zheng; Pinaki Mazumder (IEEE Trans. Computers, 2017)

Energy-Efficient Hardware Architecture of Self-Organizing Map for ECG Clustering in 65-nm CMOS. - Jaeyoung Kim; Pinaki Mazumder (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase Decoding of BCH Codes. - Nan Zheng; Pinaki Mazumder (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells. - Nan Zheng; Pinaki Mazumder (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks. - Nan Zheng; Pinaki Mazumder (ISCAS, 2018)

A Low-Power Circuit for Adaptive Dynamic Programming. - Nan Zheng; Pinaki Mazumder (VLSID, 2018)

A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming. - Nan Zheng; Pinaki Mazumder (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Online Supervised Learning for Hardware-Based Multilayer Spiking Neural Networks Through the Modulation of Weight-Dependent Spike-Timing-Dependent Plasticity. - Nan Zheng; Pinaki Mazumder (IEEE Trans. Neural Networks Learn. Syst., 2018)

Spoof Plasmon Interconnects - Communications Beyond RC Limit. - Soumitra Roy Joy; Mikhail Erementchouk; Hao Yu 001; Pinaki Mazumder (IEEE Trans. Commun., 2019)

Convolutional Neural Network Design for Breast Cancer Medical Image Classification. - Yongbin Yu 001; Favour Ekong; Pinaki Mazumder (ICCT, 2020)

Process Variation in Spoof Plasmon Interconnect: Consequences and Compensations. - Md. Faizul Bari; Soumitra Roy Joy; Md. Zunaid Baten; Pinaki Mazumder (RWS, 2020)

Terahertz Quantum Cryptography. - Carlo Ottaviani; Matthew J. Woolley; Misha Erementchouk; John F. Federici; Pinaki Mazumder; Stefano Pirandola; Christian Weedbrook (IEEE J. Sel. Areas Commun., 2020)

Navigating the Seismic Shift of Post-Moore Computer Systems Design. - Anindya Banerjee 001; Sankar Basu; Erik Brunvand; Pinaki Mazumder; Rance Cleaveland; Gurdip Singh; Margaret Martonosi; Fernanda Pembleton (IEEE Micro, 2021)

Dynamic Pinning Synchronization of Fuzzy-Dependent-Switched Coupled Memristive Neural Networks With Mismatched Dimensions on Time Scales. - Xiangxiang Wang; Yongbin Yu 001; Jingye Cai; Shouming Zhong; Nijing Yang; Kaibo Shi; Pinaki Mazumder; Tashi Nyima (IEEE Trans. Fuzzy Syst., 2022)

Self-contained relaxation-based dynamical Ising machines. - Mikhail Erementchouk; Aditya Shukla; Pinaki Mazumder (CoRR, 2023)

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. - Matthew Guthaus; Christopher Batten; Erik Brunvand; Pierre-Emmanuel Gaillardon; David M. Harris; Rajit Manohar; Pinaki Mazumder; Larry T. Pileggi; James E. Stine (CoRR, 2023)

Custom CMOS Ising Machine Based on Relaxed Burer-Monteiro-Zhang Heuristic. - Aditya Shukla; Mikhail Erementchouk; Pinaki Mazumder (IEEE Trans. Computers, 2023)

Non-binary dynamical Ising machines for combinatorial optimization. - Aditya Shukla; Mikhail Erementchouk; Pinaki Mazumder (CoRR, 2024)

Scalable almost-linear dynamical Ising machines. - Aditya Shukla; Mikhail Erementchouk; Pinaki Mazumder (Nat. Comput., 2025)