MDCT spectrum separation: Catching the fine spectral structures for stereo coding. - Shuhua Zhang; Weibei Dou; Ping Chi; Huazhong Yang (ICASSP, 2010)

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. - Ping Chi; Cong Xu 002; Tao Zhang 032; Xiangyu Dong 001; Yuan Xie 001 (ICCAD, 2014)

Making B+-tree efficient in PCM-based main memory. - Ping Chi; Wang-Chien Lee; Yuan Xie 001 (ISLPED, 2014)

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. - Ping Chi; Cong Xu 002; Xiaochun Zhu; Yuan Xie 001 (ISQED, 2014)

Leveraging nonvolatility for architecture design with emerging NVM. - Shuangchen Li; Ping Chi; Jishen Zhao; Kwang-Ting Cheng; Yuan Xie 001 (NVMSA, 2015)

Memory and Storage System Design with Nonvolatile Memory Technologies. - Jishen Zhao; Cong Xu 002; Ping Chi; Yuan Xie 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Architecture design with STT-RAM: Opportunities and challenges. - Ping Chi; Shuangchen Li; Yuanqing Cheng; Yu Lu; Seung-Hyuk Kang; Yuan Xie 001 (ASP-DAC, 2016)

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. - Ping Chi; Shuangchen Li; Cong Xu 002; Tao Zhang 032; Jishen Zhao; Yongpan Liu; Yu Wang 002; Yuan Xie 001 (ISCA, 2016)

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. - Yu Ji 002; Youhui Zhang; Shuangchen Li; Ping Chi; Cihang Jiang; Peng Qu; Yuan Xie 001; Wenguang Chen (MICRO, 2016)

Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory. - Ping Chi; Wang-Chien Lee; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives - Ping Chi (2016)

Building energy-efficient multi-level cell STT-RAM caches with data compression. - Liu Liu 017; Ping Chi; Shuangchen Li; Yuanqing Cheng; Yuan Xie 001 (ASP-DAC, 2017)

Approximate image storage with multi-level cell STT-MRAM main memory. - Hengyu Zhao; Linuo Xue; Ping Chi; Jishen Zhao (ICCAD, 2017)