A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension. - Chin-Fu Li; Chang-Ming Lai; Ping-Chuan Chiang; Po-Chiun Huang (ISOCC, 2011)

100Gb/s ethernet chipsets in 65nm CMOS technology. - Jhih-Yu Jiang; Ping-Chuan Chiang; Hao-Wei Hung; Chen-Lun Lin; Ty Yoon; Jri Lee (ISSCC, 2013)

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. - Ping-Chuan Chiang; Hao-Wei Hung; Hsiang-Yun Chu; Guan-Sing Chen; Jri Lee (ISSCC, 2014)

56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. - Jri Lee; Ping-Chuan Chiang; Chih-Chi Weng (VLSIC, 2015)

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. - Ping-Chuan Chiang; Jhih-Yu Jiang; Hao-Wei Hung; Chin-Yang Wu; Gaun-Sing Chen; Jri Lee (IEEE J. Solid State Circuits, 2015)

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. - Jri Lee; Ping-Chuan Chiang; Pen-Jui Peng; Li-Yang Chen; Chih-Chi Weng (IEEE J. Solid State Circuits, 2015)

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS. - Kok Lim Chan; Kee Hian Tan; Yohan Frans; Jay Im; Parag Upadhyaya; Siok-Wei Lim; Arianne Roldan; Nakul Narang; Chin Yang Koay; Hongyuan Zhao; Ping-Chuan Chiang; Ken Chang (IEEE J. Solid State Circuits, 2017)

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. - Marc Erett; Declan Carey; James Hudner; Ronan Casey; Kevin Geary; Pedro Neto 001; Mayank Raj; Scott McLeod; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; et al. (ISSCC, 2018)

A 112-GB/S PAM4 Transmitter in 16NM FinFET. - Kee Hian Tan; Ping-Chuan Chiang; Yipeng Wang 003; Haibing Zhao; Arianne Roldan; Hongyuan Zhao; Nakul Narang; Siok-Wei Lim; Declan Carey; Sai Lalith Chaitanya Ambatipudi; Parag Upadhyaya; Yohan Frans; et al. (VLSI Circuits, 2018)

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. - Marc Erett; Declan Carey; Ronan Casey; James Hudner; Kevin Geary; Ted Lee; Mayank Raj; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; Haibing Zhao; et al. (CICC, 2019)

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (ECOC, 2020)

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (IEEE J. Solid State Circuits, 2020)