A Simple Fiber Bragg Grating-Based Sensor Network Architecture with Self-Protecting and Monitoring Functions. - Chien-Hung Yeh; Chi-Wai Chow; Ping-Chun Wu; Fan-Gang Tseng (Sensors, 2011)

Measurement of Organic Chemical Refractive Indexes Using an Optical Time-Domain Reflectometer. - Chien-Hung Yeh; Chi-Wai Chow; Jiun-Yu Sung; Ping-Chun Wu; Wha-Tzong Whang; Fan-Gang Tseng (Sensors, 2012)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips. - Hung-Hsi Hsu; Tai-Hao Wen; Ping-Chun Wu; Chuan-Jia Jhang; De-Qi You; Ping-Cheng Chen; Meng-Fan Chang (MWSCAS, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. - Win-San Khwa; Ping-Chun Wu; Jui-Jen Wu; Jian-Wei Su; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; Ren-Shuo Liu; et al. (ISSCC, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

Optimizing Session-Aware Recommenders: A Deep Dive into GRU-Based Latent Interaction Integration. - Ming-Yen Lin; Ping-Chun Wu; Sue-Chen Hsueh (Future Internet, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. - Win-San Khwa; Ping-Chun Wu; Jian-Wei Su; Chiao-Yen Cheng; Jun-Ming Hsu; Yu-Chen Chen; Le-Jung Hsieh; Jyun-Cheng Bai; Yu-Sheng Kao; Tsung-Han Lou; Ashwin Sanjay Lele; Jui-Jen Wu; et al. (ISSCC, 2025)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)