Temporal floorplanning using 3D-subTCG. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang; Hsin-Lung Chen (ASP-DAC, 2004)

Temporal floorplanning using the T-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ICCAD, 2004)

A routing algorithm for flip-chip design. - Jia-Wei Fang; I-Jye Lin; Ping-Hung Yuh; Yao-Wen Chang; Jyh-Herng Wang (ICCAD, 2005)

Joint exploration of architectural and physical design spaces with thermal consideration. - Yen-Wei Wu; Chia-Lin Yang; Ping-Hung Yuh; Yao-Wen Chang (ISLPED, 2005)

Placement of digital microfluidic biochips using the t-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (DAC, 2006)

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Denny Liu (DAC, 2007)

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ICCAD, 2007)

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. - Chi-Feng Li; Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ISLPED, 2007)

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM J. Emerg. Technol. Comput. Syst., 2007)

Temporal floorplanning using the three-dimensional transitive closure subGraph. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2007)

A progressive-ILP based routing algorithm for cross-referencing biochips. - Ping-Hung Yuh; Sachin S. Sapatnekar; Chia-Lin Yang; Yao-Wen Chang (DAC, 2008)

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Tien-Yueh Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. - Ping-Hung Yuh; Sachin S. Sapatnekar; Chia-Lin Yang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

T-trees: A tree-based representation for temporal and three-dimensional floorplanning. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2009)

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. - Ping-Hung Yuh; Chia-Lin Yang; Chi-Feng Li; Chung-Hsiang Lin (ACM Trans. Design Autom. Electr. Syst., 2009)

Application-specific 3D Network-on-Chip design using simulated allocation. - Pingqiang Zhou; Ping-Hung Yuh; Sachin S. Sapatnekar (ASP-DAC, 2010)

A SAT-based routing algorithm for cross-referencing biochips. - Ping-Hung Yuh; Cliff Chiung-Yu Lin; Tsung-Wei Huang; Tsung-Yi Ho; Chia-Lin Yang; Yao-Wen Chang (SLIP, 2011)

Optimized 3D Network-on-Chip Design Using Simulated Allocation. - Pingqiang Zhou; Ping-Hung Yuh; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2012)

Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes. - Keh-Jeng Chang; Shih-Hao Lee; Kuo-Fu Lee; Ping-Hung Yuh; Ho-Che Yu; Wen-Cheng Huang; Victor C. Y. Chang (VLSI-DAT, 2015)