A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. - Ping Lu 002; Pietro Andreani; Antonio Liscidini (ESSCIRC, 2011)

A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. - Mohammed Abdulaziz; Muhammad Shakir; Ping Lu 002; Pietro Andreani (NORCHIP, 2011)

A mixed mode design flow for multi GHz ADPLLs. - Muhammad Shakir; Mohammed Abdulaziz; Ping Lu 002; Pietro Andreani (NORCHIP, 2011)

A digital PLL with a multi-delay coarse-fine TDC. - Ying Wu 003; Ping Lu 002; Pietro Andreani (NORCHIP, 2011)

A 0.13µm CMOS ΔΣ PLL FM transmitter. - Ying Wu 003; Xiaodong Liu; Dawei Ye; Vijay Viswam; Lin Zhu; Ping Lu 002; Dejan Radjen; Henrik Sjöland (NORCHIP, 2011)

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter. - Ping Lu 002; Ying Wu 003; Pietro Andreani (ISCAS, 2012)

A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. - Ping Lu 002; Pietro Andreani; Antonio Liscidini (NORCHIP, 2012)

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. - Ping Lu 002; Antonio Liscidini; Pietro Andreani (IEEE J. Solid State Circuits, 2012)

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. - Dawei Ye; Ping Lu 002; Pietro Andreani; Ronan A. R. van der Zee (ISCAS, 2013)

A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping. - Ping Lu 002; Pietro Andreani (ISCAS, 2014)

A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio. - Ji Wang; Manuel Bejarano Carmona; Helgi Hall; Dejan Radjen; Ping Lu 002 (NORCHIP, 2014)

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. - Ahmed Mahmoud; Pietro Andreani; Ping Lu 002 (NORCAS, 2015)

A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. - Ying Wu 003; Mina Shahmohammadi; Yue Chen; Ping Lu 002; Robert Bogdan Staszewski (ESSCIRC, 2016)

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration. - Ping Lu 002; Ying Wu 003; Pietro Andreani (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. - Ying Wu 003; Mina Shahmohammadi; Yue Chen; Ping Lu 002; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2017)

A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction. - Ying Wu 003; Ping Lu 002; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)