A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. - Ming-Zhang Kuo; Osamu Takahashi; Ping-Lin Yang; Cheng-Chung Lin; Min-Jer Wang; Ping-Wei Wang; Sang H. Dhong (CICC, 2013)

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Hank Cheng; Wei-Min Chan; Hung-Jen Liao; Quincy Li; Stanley Chang; Sreedhar Natarajan; Robin Lee; Ping-Wei Wang; Shyue-Shyh Lin; Chung-Cheng Wu; et al. (ISSCC, 2013)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology. - Nick Zhang; Young Suk Kim; Peter Hsu; Samsoo Kim; Derek Tao; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)