A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. - Ping-Ying Wang; Hsiang Ji Hsieh; Yung-Yu Lin; Meng-Ta Yang; Hsueh-Wu Kao (ISCAS (5), 2005)

Chaos in delay locked loop. - Ping-Ying Wang; C.-H. Chou; Hsueh-Wu Kao (ISCAS, 2006)

RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. - Ping-Ying Wang; Meng-Ta Yang; Shang-Ping Chen; Meng-Hsueh Lin; Jing-Bing Yang (ISSCC, 2007)

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. - Ping-Ying Wang; Jing-Hong Conan Zhan; Hsiang-Hui Chang; Bing-Yu Hsieh (CICC, 2008)

A fractional spur reduction technique for RF TDC-based all digital PLLs. - Ping-Ying Wang; Hsiang-Hui Chang; Jing-Hong Conan Zhan (ESSCIRC, 2008)

A charge pump-based direct frequency modulator. - Ping-Ying Wang; Hsiu-Ming Chang 001 (ISCAS, 2008)

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. - Hsiang-Hui Chang; Ping-Ying Wang; Jing-Hong Conan Zhan; Bing-Yu Hsieh (ISSCC, 2008)

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. - Ping-Ying Wang; Jing-Hong Conan Zhan; Hsiang-Hui Chang; Hsiu-Ming (Sherman) Chang (IEEE J. Solid State Circuits, 2009)

All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL. - Ping-Ying Wang; Chia-Huang Fu (ESSCIRC, 2010)

An all-digital built-in self-test technique for transfer function characterization of RF PLLs. - Ping-Ying Wang; Hsiu-Ming Chang 001; Kwang-Ting Cheng (DATE, 2011)

An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. - Yi-Chieh Huang; Ping-Ying Wang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. - Yi-Chieh Huang; Che-Fu Liang; Hsien-Sheng Huang; Ping-Ying Wang (ISSCC, 2014)

A 1V fractional-N PLL with nonlinearity-insensitive modulator. - Yi-Chieh Huang; Che-Fu Liang; Ping-Ying Wang (A-SSCC, 2015)

10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. - Che-Fu Liang; Ping-Ying Wang (ISSCC, 2015)