Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). - Pingakshya Goswami; Dinesh Bhatia (FPGA, 2016)

MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (FPGA, 2020)

Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. - Pingakshya Goswami; Dinesh Bhatia (CoRR, 2020)

Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. - Pingakshya Goswami; Dinesh Bhatia (ISQED, 2022)

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (LASCAS, 2022)

Robust Estimation of FPGA Resources and Performance from CNN Models. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (VLSID, 2022)

Application of Machine Learning in FPGA EDA Tool Development. - Pingakshya Goswami; Dinesh Bhatia (IEEE Access, 2023)

Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. - Pingakshya Goswami; Benjamin Carrión Schäfer; Dinesh Bhatia (Integr., 2023)