A CMOS general-purpose sampled-data analogue microprocessor. - Piotr Dudek; Peter J. Hicks (ISCAS, 2000)

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. - Piotr Dudek; Stanislaw Szczepanski; John V. Hatfield (IEEE J. Solid State Circuits, 2000)

An analogue SIMD focal-plane processor array. - Piotr Dudek; Peter J. Hicks (ISCAS (4), 2001)

A flexible global readout architecture for an analogue SIMD vision chip. - Piotr Dudek (ISCAS (3), 2003)

A 39×48 general-purpose focal-plane processor array integrated circuit. - Piotr Dudek (ISCAS (5), 2004)

An area and power efficient discrete-time chaos generator circuit. - Piotr Dudek; V. D. Juncu (ECCTD, 2005)

Architecture of asynchronous cellular processor array for image skeletonization. - Aliaksei Lopich; Piotr Dudek (ECCTD, 2005)

Implementation of SIMD vision chip with 128×128 array of analogue processing elements. - Piotr Dudek (ISCAS (6), 2005)

A general-purpose processor-per-pixel analog SIMD vision chip. - Piotr Dudek; Peter J. Hicks (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Simple Analogue VLSI Circuit of a Cortical Neuron. - Jayawan H. B. Wijekoon; Piotr Dudek (ICECS, 2006)

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. - Alexey Lopich; Piotr Dudek (ISCAS, 2006)

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays. - Piotr Dudek (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

On chip implementation of a pixel-parallel approach for retinal vessel tree extraction. - Carmen Alonso-Montes; Piotr Dudek; David López Vilariño; Manuel G. Penedo (ECCTD, 2007)

Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. - Alexey Lopich; Piotr Dudek (ECCTD, 2007)

Implementation of multi-layer leaky integrator networks on a cellular processor array. - David Robert Wallace Barr; Piotr Dudek; Jonathan M. Chambers; Kevin N. Gurney (IJCNN, 2007)

Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. - Jayawan H. B. Wijekoon; Piotr Dudek (IJCNN, 2007)

Evolution of Pixel Level Snakes towards an efficient hardware implementation. - David López Vilariño; Piotr Dudek (ISCAS, 2007)

Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array. - Martin Hülse; David Robert Wallace Barr; Piotr Dudek (Automata, 2008)

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. - Jim Harkin; Fearghal Morgan; Steve Hall; Piotr Dudek; Thomas Dowrick; Liam McDaid (FPL, 2008)

ASPA: Focal Plane digital processor array with asynchronous processing capabilities. - Alexey Lopich; Piotr Dudek (ISCAS, 2008)

Focal-plane moving object segmentation for realtime video surveillance. - David López Vilariño; Piotr Dudek; Diego Cabello (ISCAS, 2008)

Integrated circuit implementation of a cortical neuron. - Jayawan H. B. Wijekoon; Piotr Dudek (ISCAS, 2008)

Fast retinal vessel tree extraction: A pixel parallel approach. - Carmen Alonso-Montes; David López Vilariño; Piotr Dudek; Manuel G. Penedo (Int. J. Circuit Theory Appl., 2008)

Compact silicon neuron circuit with spiking and bursting behaviour. - Jayawan H. B. Wijekoon; Piotr Dudek (Neural Networks, 2008)

A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. - Piotr Dudek; Alexey Lopich; Viktor Gruev (ECCTD, 2009)

APRON: A Cellular Processor Array Simulation and Hardware Design Tool. - David Robert Wallace Barr; Piotr Dudek (EURASIP J. Adv. Signal Process., 2009)

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing. - Alexey Lopich; Piotr Dudek (J. Signal Process. Syst., 2009)

Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. - Kevin Brohan; Kevin N. Gurney; Piotr Dudek (ICANN (2), 2010)

An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology. - Alexey Lopich; Piotr Dudek (ISCAS, 2010)

Demonstration of a low power image processing system using a SCAMP3 vision chip. - Stephen J. Carey; David Robert Wallace Barr; Piotr Dudek (ICDSC, 2011)

Self-Organizing Neural Population Coding for improving robotic visuomotor coordination. - Tao Zhou; Piotr Dudek; Bertram E. Shi (IJCNN, 2011)

Confession session: Learning from others mistakes. - Pamela Abshire; Amine Bermak; Raphael Berner; Gert Cauwenberghs; Shoushun Chen; Jennifer Blain Christen; Timothy G. Constandinou; Eugenio Culurciello; Marc Dandin; Timir Datta; Tobi Delbruck; Piotr Dudek; et al. (ISCAS, 2011)

A processor element for a mixed signal cellular processor array vision chip. - Stephen J. Carey; Alexey Lopich; Piotr Dudek (ISCAS, 2011)

Live demonstration: Real-time image processing on ASPA2 vision system. - Alexey Lopich; David Robert Wallace Barr; Bin Wang; Piotr Dudek (ISCAS, 2011)

Analogue CMOS circuit implementation of a dopamine modulated synapse. - Jayawan H. B. Wijekoon; Piotr Dudek (ISCAS, 2011)

Architecture and design of a programmable 3D-integrated cellular processor array for image processing. - Alexey Lopich; Piotr Dudek (VLSI-SoC, 2011)

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. - Alexey Lopich; Piotr Dudek (Int. J. Circuit Theory Appl., 2011)

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. - Alexey Lopich; Piotr Dudek (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A field programmable array core for image processing (abstract only). - Declan Walsh; Piotr Dudek (FPGA, 2012)

Development of robot self-identification based on visuomotor prediction. - Tao Zhou; Piotr Dudek; Bertram E. Shi (ICDL-EPIROB, 2012)

Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. - Stephen J. Carey; David Robert Wallace Barr; Bin Wang; Alexey Lopich; Piotr Dudek (ICECS, 2012)

Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization. - Przemyslaw Mroszczyk; Piotr Dudek (ISCAS, 2012)

Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC. - Jayawan H. B. Wijekoon; Piotr Dudek (ISCAS, 2012)

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. - Alexey Lopich; Piotr Dudek (CICC, 2013)

Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays. - Przemyslaw Mroszczyk; Piotr Dudek (ECCTD, 2013)

AMBER: Adapting multi-resolution background extractor. - Bin Wang; Piotr Dudek (ICIP, 2013)

Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters. - Przemyslaw Mroszczyk; Piotr Dudek (NEWCAS, 2013)

Metachronal Waves in Cellular Automata: Cilia-Like Manipulation in Actuator Arrays. - Ioannis Georgilas; Andrew Adamatzky; David Robert Wallace Barr; Piotr Dudek; Chris Melhuish (NICSO, 2013)

A Smart Surface Simulation Environment. - David Robert Wallace Barr; Declan Walsh; Piotr Dudek (SMC, 2013)

Low power high-performance smart camera system based on SCAMP vision sensor. - Stephen J. Carey; David Robert Wallace Barr; Piotr Dudek (J. Syst. Archit., 2013)

A Fast Self-Tuning Background Subtraction Algorithm. - Bin Wang; Piotr Dudek (CVPR Workshops, 2014)

Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision. - Stephen J. Carey; David Robert Wallace Barr; Bin Wang; Alexey Lopich; Piotr Dudek (ISCAS, 2014)

Characterization of processing errors on analog fully-programmable cellular sensor-processor arrays. - Stephen J. Carey; Ákos Zarándy; Piotr Dudek (ISCAS, 2014)

The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits. - Przemyslaw Mroszczyk; Piotr Dudek (ISCAS, 2014)

Tunable CMOS Delay Gate With Improved Matching Properties. - Przemyslaw Mroszczyk; Piotr Dudek (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Pixel interlacing to trade off the resolution of a cellular processor array against more registers. - Julien N. P. Martel; Miguel Chau; Matthew Cook 001; Piotr Dudek (ECCTD, 2015)

Gradient-descent-based learning in memristive crossbar arrays. - Manu V. Nair; Piotr Dudek (IJCNN, 2015)

Toward joint approximate inference of visual quantities on cellular processor arrays. - Julien N. P. Martel; Miguel Chau; Piotr Dudek; Matthew Cook 001 (ISCAS, 2015)

An event-driven massively parallel fine-grained processor array. - Declan Walsh; Piotr Dudek (ISCAS, 2015)

Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. - Przemyslaw Mroszczyk; Piotr Dudek (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Demonstration of Tracking using Dynamic Neural Fields on a Programmable Vision Chip: Demo. - Julien N. P. Martel; Yulia Sandamirskaya; Piotr Dudek (ICDSC, 2016)

Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip. - Julien N. P. Martel; Lorenz K. Müller; Stephen J. Carey; Piotr Dudek (ISCAS, 2016)

Visual Odometry for Pixel Processor Arrays. - Laurie Bose; Jianing Chen; Stephen J. Carey; Piotr Dudek; Walterio W. Mayol-Cuevas (ICCV, 2017)

Tracking control of a UAV with a parallel visual processor. - Colin Greatwood; Laurie Bose; Thomas S. Richardson 002; Walterio W. Mayol-Cuevas; Jianing Chen; Stephen J. Carey; Piotr Dudek (IROS, 2017)

High-speed depth from focus on a programmable vision chip using a focus tunable lens. - Julien N. P. Martel; Lorenz K. Müller; Stephen J. Carey; Piotr Dudek (ISCAS, 2017)

Live demonstration: Depth from focus on a focal plane processor using a focus tunable liquid lens. - Julien N. P. Martel; Lorenz K. Müller; Stephen J. Carey; Jonathan Müller; Yulia Sandamirskaya; Piotr Dudek (ISCAS, 2017)

Scamp5d Vision System and Development Framework. - Jianing Chen; Stephen J. Carey; Piotr Dudek (ICDSC, 2018)

Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array. - Colin Greatwood; Laurie Bose; Thomas Richardson 002; Walterio W. Mayol-Cuevas; Jianing Chen; Stephen J. Carey; Piotr Dudek (IROS, 2018)

Real-Time Depth From Focus on a Programmable Focal Plane Processor. - Julien N. P. Martel; Lorenz K. Müller; Stephen J. Carey; Jonathan Müller; Yulia Sandamirskaya; Piotr Dudek (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Live Demonstration: Digit Recognition on Pixel Processor Arrays. - Laurie Bose; Jianing Chen; Stephen J. Carey; Piotr Dudek; Walterio W. Mayol-Cuevas (CVPR Workshops, 2019)

A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. - Laurie Bose; Piotr Dudek; Jianing Chen; Stephen J. Carey; Walterio W. Mayol-Cuevas (ICCV, 2019)

High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array. - Yanan Liu; Laurie Bose; Jianing Chen; Stephen J. Carey; Piotr Dudek; Walterio W. Mayol-Cuevas (BMVC, 2020)

Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. - Laurie Bose; Piotr Dudek; Jianing Chen; Stephen J. Carey; Walterio W. Mayol-Cuevas (ECCV (29), 2020)

Proximity Estimation Using Vision Features Computed On Sensor. - Jianing Chen; Yanan Liu; Stephen J. Carey; Piotr Dudek (ICRA, 2020)

Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array. - Stephen J. Carey; Laurie Bose; Thomas S. Richardson 002; Walterio W. Mayol-Cuevas; Jianing Chen; Piotr Dudek (ISCAS, 2020)

Lessons Learned the Hard Way. - Tobi Delbruck; Ibrahim Abe M. Elfadel; Shahzad Muzaffar; Germain Haessig; Bo Wang 012; Amine Bermak; Rui Graca; Luis A. Camuñas-Mesa; Bathiya Senevirathna; Pamela Abshire; Bernabé Linares-Barranco; Saeed Afshar; et al. (ISCAS, 2020)

A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting. - Germain Haessig; Daniel García-Lesta; Gregor Lenz; Ryad Benosman; Piotr Dudek (ISCAS, 2020)

Visual Odometry Using Pixel Processor Arrays for Unmanned Aerial Systems in GPS Denied Environments. - Alexander McConville; Laurie Bose; Robert Clarke; Walterio W. Mayol-Cuevas; Jianing Chen; Colin Greatwood; Stephen J. Carey; Piotr Dudek; Thomas Richardson 002 (Frontiers Robotics AI, 2020)

Neural Sensors: Learning Pixel Exposures for HDR Imaging and Video Compressive Sensing With Programmable Sensors. - Julien N. P. Martel; Lorenz K. Müller; Stephen J. Carey; Piotr Dudek; Gordon Wetzstein (IEEE Trans. Pattern Anal. Mach. Intell., 2020)

Bringing A Robot Simulator to the SCAMP Vision System. - Yanan Liu; Jianing Chen; Laurie Bose; Piotr Dudek; Walterio W. Mayol-Cuevas (CoRR, 2021)

Direct Servo Control from In-Sensor CNN Inference with A Pixel Processor Array. - Yanan Liu; Jianing Chen; Laurie Bose; Piotr Dudek; Walterio W. Mayol-Cuevas (CoRR, 2021)

Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array. - Yanan Liu; Laurie Bose; Colin Greatwood; Jianing Chen; Rui Fan 001; Thomas Richardson 002; Stephen J. Carey; Piotr Dudek; Walterio W. Mayol-Cuevas (IET Image Process., 2021)

MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. - Haley M. So; Julien N. P. Martel; Gordon Wetzstein; Piotr Dudek (ICCP, 2022)

Pixel Processor Arrays For Low Latency Gaze Estimation. - Laurie Bose; Jianing Chen; Stephen J. Carey; Piotr Dudek (VR Workshops, 2022)

Sensor-level computer vision with pixel processor arrays for agile robots. - Piotr Dudek; Tom Richardson 002; Laurie Bose; Stephen J. Carey; Jianing Chen; Colin Greatwood; Yanan Liu; Walterio W. Mayol-Cuevas (Sci. Robotics, 2022)

Live Demonstration: SCAMP-7. - Laurie Bose; Piotr Dudek; Stephen J. Carey; Jianing Chen (CVPR Workshops, 2023)

PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. - Haley M. So; Laurie Bose; Piotr Dudek; Gordon Wetzstein (CVPR, 2024)

Factor Machine: Mixed-signal Architecture for Fine-Grained Graph-Based Computing. - Piotr Dudek (CoRR, 2024)

Mapping Image Transformations Onto Pixel Processor Arrays. - Laurie Bose; Piotr Dudek (CoRR, 2024)

Descriptor-In-Pixel : Point-Feature Tracking For Pixel Processor Arrays. - Laurie Bose; Jianing Chen; Piotr Dudek (CVPR, 2025)

Demo : Point-Feature Tracking for Pixel Processor Arrays. - Laurie Bose; Piotr Dudek (CVPR Workshops, 2025)

Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem. - Maciej Lewandowski; Piotr Dudek (ISCAS, 2025)

Digital Implementation of a Spiking/Bursting Neuron Model with Low Resources. - Ziyao Zhang; Piotr Dudek; Jayawan H. B. Wijekoon (ISCAS, 2025)

A General-Purpose Neuromorphic Sensor based on Spiketrum Algorithm: Hardware Details and Real-life Applications. - MHD Anas Alsakkal; Runze Wang; Jayawan H. B. Wijekoon; Piotr Dudek (CoRR, 2025)