New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices. - Piotr Ratuszniak; Oleg Maslennikow (IMCSIT, 2009)

Application Specific Processors for the Autoregressive Signal Analysis. - Anatolij Sergiyenko; Oleg Maslennikow; Piotr Ratuszniak; Natalia Maslennikowa; Adam Tomas (PPAM (1), 2009)

Processor Array Design with the Use of Genetic Algorithm. - Piotr Ratuszniak (LSSC, 2011)

Hybrid Genetic Algorithm for Allocation Mapping in Processor Array Design. - Piotr Ratuszniak (LSSC, 2013)

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. - Duncan J. M. Moss; Krishnan Srivatsan; Eriko Nurvitadhi; Piotr Ratuszniak; Chris Johnson; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPGA, 2018)

DAPHNE: An Open and Extensible System Infrastructure for Integrated Data Analysis Pipelines. - Patrick Damme; Marius Birkenbach; Constantinos Bitsakos; Matthias Boehm 001; Philippe Bonnet; Florina M. Ciorba; Mark Dokter; Pawel Dowgiallo; Ahmed Eleliemy; Christian Faerber; Georgios I. Goumas; Dirk Habich; et al. (CIDR, 2022)

Lightweight deep neural network for navigation safety assessment system detecting small floating objects on sea surface. - Miroslaw Lacki; Piotr Ratuszniak (EUROCON, 2025)

Big Data Acceleration on Tightly Coupled FPGA: An Alternating Least Squares inference Case Study. - Piotr Ratuszniak; Krishnan Srivatsan; Ilya Burylov; Ramesh Illikkal; Chong Yeol Nah; Miroslaw Lacki (EUROCON, 2025)