Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. - Michael Merrett; Plamen Asenov; Yangang Wang; Mark Zwolinski; Dave Reid; Campbell Millar; Scott Roy; Zhenyu Liu; Stephen B. Furber; Asen Asenov (DATE, 2011)

An advanced statistical compact model strategy for SRAM simulation at reduced VDD. - Plamen Asenov; Dave Reid; Scott Roy; Campbell Millar; Asen Asenov (ESSDERC, 2012)

Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models. - Plamen Asenov; David New; Dave Reid; Campbell Millar; Scott Roy; Asen Asenov (ICICDT, 2013)

Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits. - A. Asenov; Jie Ding; Dave Reid; Plamen Asenov; Salvatore M. Amoroso; Fikru Adamu-Lema; Louis Gerrer (ISCAS, 2015)

Nanowire transistor solutions for 5nm and beyond. - A. Asenov; Yangang Wang; Binjie Cheng; Xingsheng Wang; Plamen Asenov; Talib Al-Ameri; Vihar P. Georgiev (ISQED, 2016)

TCAD based Design-Technology Co-Optimisations in advanced technology nodes. - Asen Asenov; Karim El Sayed; Ricardo Borges; Plamen Asenov; Campbell Millar; Terry Ma (VLSI-DAT, 2017)

Exploring Power Savings of Gate-All-Around Cryogenic Technology. - Victor Moroz; Alexei Svizhenko; Munkang Choi; Plamen Asenov; Jaehyun Lee (VLSI Technology and Circuits, 2023)

Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development. - Xi-Wei Lin; Salvatore M. Amoroso; Ko-Hsin Lee; Meng Hsuan Ke; Tue Gunst; Pavel Tikhomirov; Plamen Asenov (IMW, 2024)

Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology. - Leitao Liu; Jingtian Fang; Ashish Pal; Plamen Asenov; Mohit Bajaj; Bei Deng; Xi-Wei Lin; Souvik Mahapatra; Subi Kengeri; El Mehdi Bazizi (IRPS, 2024)