Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design. - Kuei-Cheng Lin; Hwann-Kaeo Chiou; Po-Chang Wu; Chu-Jung Sha; Chun-Lin Ko; Da-Chiang Chang; Ying-Zong Juang (VLSI-DAT, 2012)

Novel automatic offset cancellation approach for capacitive CMOS MEMS accelerometers. - Po-Chang Wu; Bin-Da Liu; Yu-Chen Teng; Chih-Yuan Yeh; Sheng-Hsiang Tseng; Hann-Huei Tsai; Ying-Zong Juang (ISCE, 2013)

5-GHz SiGe linearity power amplifier using integrated feedforward architecture for WLAN applications. - Kuei-Cheng Lin; Hwann-Kaeo Chiou; Po-Chang Wu; Hann-Huei Tsai; Ying-Zong Juang (ISCAS, 2014)

Efficient Parallel Muti-pattern Matching Using GPGPU Acceleration for Packet Filtering. - Che-Lun Hung; Po-Chang Wu; Hsiao-Hsi Wang; Chun-Yuan Lin (HPCC/CSS/ICESS, 2015)

Design of a 0.6-V 0.2-mW CMOS MEMS accelerometer. - Po-Chang Wu; Bin-Da Liu; Chih-Yuan Yeh; Sheng-Hsiang Tseng; Hann-Huei Tsai; Ying-Zong Juang (ICCE-TW, 2015)

Low-frequency noise reduction technique for accelerometer readout circuit. - Po-Chang Wu; Chih-Yuan Yeh; Hann-Huei Tsai; Ying-Zong Juang (APCCAS, 2016)

A low power and low noise CMOS chopper amplifier for use in capacitive type accelerometer. - Chih-Yuan Yeh; Jung-Tang Huang; Po-Chang Wu; Hann-Huei Tsai; Ying-Zong Juang (APCCAS, 2016)

Dielectric characterization and voltage holding ratio of blue-phase cells. - Po-Chang Wu; Hsuan-Tsung Hsu; Hsin-Li Chen; Wei Lee 002 (Displays, 2016)

An Efficient GPU-Based Multiple Pattern Matching Algorithm for Packet Filtering. - Che-Lun Hung; Chun-Yuan Lin; Po-Chang Wu (J. Signal Process. Syst., 2017)

A 2.5D mm-size Wafer-level CMOS-IPD Wireless Power Transfer Receiver Using Cross-coupled and Self-biasing Topology for Implantable Biomedical System. - Kuei-Cheng Lin; Po-Chang Wu; Yu-Chen Liu; Hann-Huei Tsai; Ying-Zong Juang (APCCAS, 2019)

A Low-Cost 70Mbps Optical Detector Design For Optocoupler Application. - Yu-Chen Liu; Po-Chang Wu; Hann-Huei Tsai; Ying-Zong Juang (APCCAS, 2019)

A low-power monolithic three-axis accelerometer with automatically sensor offset compensated and interface circuit. - Chih-Yuan Yeh; Jung-Tang Huang; Sheng-Hsiang Tseng; Po-Chang Wu; Hann-Huei Tsai; Ying-Zong Juang (Microelectron. J., 2019)

Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design. - Tzu-Wei Wang; Po-Chang Wu; Mark Po-Hung Lin (DAC, 2020)

A Low-Power Low-Noise Monolithic Accelerometer with Automatic Sensor Offset Calibration. - Chih-Yuan Yeh; Jung-Tang Huang; Sheng-Hsiang Tseng; Po-Chang Wu; Hann-Huei Tsai; Ying-Zong Juang (Microelectron. J., 2020)

A 0.01-to-2.6-GHz Two-Fold Current Reuse Dual Noise-Canceling LNA Achieving 6.8-K Noise Temperature for Quantum Applications. - Mahesh Kumar Chaubey; Chih-Cheng Lin; Yin-Cheng Chang; Po-Chang Wu; Hann-Huei Tsai; Shawn S. H. Hsu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout. - Mahesh Kumar Chaubey; Yin-Cheng Chang; Po-Chang Wu; Hann-Huei Tsai; Shawn S. H. Hsu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)