A BiCMOS limiting amplifier for SONET OC-3. - Chorng-Kuang Wang; Po-Chiun Huang; Chen-Yi Huang (IEEE J. Solid State Circuits, 1996)

A 2-V 10.7-MHz CMOS limiting amplifier/RSSI. - Po-Chiun Huang; Yi-Huei Chen; Chorng-Kuang Wang (IEEE J. Solid State Circuits, 2000)

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier. - Po-Chiun Huang; Yi-Huei Chen; Chorng-Kuang Wang (IEEE J. Solid State Circuits, 2001)

Adaptive I/Q imbalance compensation for RF transceivers. - Hsin-Hung Chen; Jiunn-Tsair Chen; Po-Chiun Huang (GLOBECOM, 2004)

Low-power techniques for network security processors. - Yi-Ping You; Chun-Yen Tseng; Yu-Hui Huang; Po-Chiun Huang; TingTing Hwang; Sheng-Yu Hsu (ASP-DAC, 2005)

An OPLL-DDS based frequency synthesizer for DCS-1800 receiver. - Yi-Da Wu; Chang-Ming Lai; Chih-Yuan Chou; Po-Chiun Huang (ISCAS, 2006)

Joint Polynomial and Look-Up-Table Predistortion Power Amplifier Linearization. - Hsin-Hung Chen; Chih-Hung Lin; Po-Chiun Huang; Jiunn-Tsair Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay. - Shan-Chih Tsou; Chin-Fu Li; Po-Chiun Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver. - Yi-Chung Chen; Yi-Chang Wu; Po-Chiun Huang (CICC, 2007)

A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops. - Meng-Hung Shen; Po-Hsiang Lan; Po-Chiun Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Design of a process-insensitive digital controller for high-frequency DC-DC SMPS. - Po-Hsiang Lan; Chun-Yen Tseng; Po-Chiun Huang (APCCAS, 2010)

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Cheng-Wen Wu; Ching-Cheng Tien; Mike Wang (DFT, 2010)

An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems. - Chun-Yen Tseng; Li-Wen Wang; Po-Chiun Huang (IEEE J. Solid State Circuits, 2010)

A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer. - Yi-Da Wu; Chang-Ming Lai; Chao-Cheng Lee; Po-Chiun Huang (IEEE J. Solid State Circuits, 2010)

Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC. - Meng-Hung Shen; Jen-Huan Tsai; Po-Chiun Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection. - Chang-Ming Lai; Meng-Hung Shen; Geng-Yi Pan; Po-Chiun Huang (A-SSCC, 2011)

An asynchronous digitally-controlled switching converter with adaptive resolution and dynamic power saving to achieve higher than 93.5% efficiency between 5mA and 250mA load. - Po-Hsiang Lan; Tsung-Ju Yang; Po-Chiun Huang (A-SSCC, 2011)

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. - Chin-Fu Li; Chi-Ying Lee; Chen-Hsing Wang; Shu-Lin Chang; Li-Ming Denq; Chun-Chuan Chi; Hsuan-Jung Hsu; Ming-Yi Chu; Jing-Jia Liou; Shi-Yu Huang; Po-Chiun Huang; Hsi-Pin Ma; et al. (DAC, 2011)

A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS. - Chang-Ming Lai; Meng-Hung Shen; Yi-Da Wu; Kai-Hsiang Huang; Po-Chiun Huang (ISCAS, 2011)

A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension. - Chin-Fu Li; Chang-Ming Lai; Ping-Chuan Chiang; Po-Chiun Huang (ISOCC, 2011)

An implantable microsystem for studying the Parkinson's Disease. - Yung-Chan Chen; Yu-Po Lin; Tsui-Ling Hsieh; Chun-Yi Yeh; Pin-Yang Huang; Hung-Chih Chiu; Zong-Ye Wang; Wen-Yang Hsu; Po-Chiun Huang; Kea-Tiong Tang; Hsi-Pin Ma; Hsin Chen (APCCAS, 2012)

An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique. - Po-Hsiang Lan; Yao-Jun Kuo; Po-Chiun Huang (VLSI-DAT, 2012)

A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques. - Jen-Huan Tsai; Yen-Ju Chen; Yan-Fong Lai; Meng-Hung Shen; Po-Chiun Huang (VLSI-DAT, 2012)

A UWB IR timed-array radar using time-shifted direct-sampling architecture. - Chang-Ming Lai; Kai-Wen Tan; Liu-Yuan Yu; Yen-Ju Chen; Jun-Wei Huang; Shr-Chau Lai; Feng-Hsu Chung; Chia-Fung Yen; Jen-Ming Wu; Po-Chiun Huang; Keh-Jeng Chang; Shi-Yu Huang; et al. (VLSIC, 2012)

A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range. - Po-Hsiang Lan; Po-Chiun Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Power-Efficient Noise Suppression Technique Using Signal-Nulled Feedback for Low-Noise Wideband Amplifiers. - Chin-Fu Li; Shih-Chieh Chou; Guan-Hong Ke; Po-Chiun Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low Cost Calibrated DAC for High-Resolution Video Display System. - Meng-Hung Shen; Po-Chiun Huang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An implantable microsystem for long-term study on the mechanism of deep brain stimulation. - Yu-Po Lin; Hung-Chih Chiu; Pin-Yang Huang; Zong-Ye Wang; Hsiang-Hui Cheng; Po-Chiun Huang; Kea-Tiong Tang; Hsi-Pin Ma; Hsin Chen (BioCAS, 2013)

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS. - Chang-Ming Lai; Jen-Ming Wu; Po-Chiun Huang; Ta-Shun Chu (ISSCC, 2013)

Time-domain analog-to-digital converters with domino delay lines. - Chang-Ming Lai; Yi-Chung Chen; Po-Chiun Huang (VLSI-DAT, 2013)

A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique. - Po-Hsiang Lan; Tsung-Ju Yang; Po-Chiun Huang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

AC-Plus Scan Methodology for Small Delay Testing and Characterization. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Ching-Cheng Tien; Chi-Hu Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer. - Chin-Fu Li; Shih-Chieh Chou; Chang-Ming Lai; Cuei-Ling Hsieh; Jenny Yi-Chun Liu; Po-Chiun Huang (A-SSCC, 2014)

A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement. - Jen-Huan Tsai; Sheng-An Ko; Hui-Huan Wang; Chia-Wei Wang; Hsin Chen; Po-Chiun Huang (A-SSCC, 2014)

An intelligent brain machine interface with wireless micro-stimulation and neural recording. - Hung-Chih Chiu; Yi-Ting Lee; Chi-Fen Chuang; Yen-Chung Chang; Shih-Rung Yeh; Po-Chiun Huang; Hsi-Pin Ma (BHI, 2014)

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS. - Yu-Hsien Kao; Chang-Ming Lai; Jen-Ming Wu; Po-Chiun Huang; Ping-Hsuan Hsieh; Ta-Shun Chu (ISSCC, 2014)

A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver. - Cuei-Ling Hsieh; Chang-Ming Lai; Guan-Hong Ke; Jenny Yi-Chun Liu; Po-Chiun Huang (VLSI-DAT, 2014)

A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry. - Jen-Huan Tsai; Hui-Huan Wang; Yen-Ju Chen; Yen-Hsin Wei; Yo-Hsien Kao; Yang-Chi Yen; Po-Chiun Huang; Meng-Hung Shen; Hsin Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. - Jen-Huan Tsai; Sheng-An Ko; Chia-Wei Wang; Yang-Chi Yen; Hui-Huan Wang; Po-Chiun Huang; Po-Hsiang Lan; Meng-Hung Shen (IEEE J. Solid State Circuits, 2015)

A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. - Jen-Huan Tsai; Hui-Huan Wang; Yang-Chi Yen; Chang-Ming Lai; Yen-Ju Chen; Po-Chiun Huang; Ping-Hsuan Hsieh; Hsin Chen; Chao-Cheng Lee (IEEE J. Solid State Circuits, 2015)

A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL. - Meng-Hung Shen; Po-Chiun Huang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Cooperation between Distributed Power Modules for SoC Power Management. - Po-Chiun Huang; Shin-Jie Huang; Po-Hsiang Lan (IEICE Trans. Electron., 2016)

A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models. - Yu-Po Lin; Chun-Yi Yeh; Pin-Yang Huang; Zong-Ye Wang; Hsiang-Hui Cheng; Yi-Ting Li; Chi-Fen Chuang; Po-Chiun Huang; Kea-Tiong Tang; Hsi-Pin Ma; Yen-Chung Chang; Shih-Rung Yeh; et al. (IEEE Trans. Biomed. Circuits Syst., 2016)

Sleep Apnea Detection Based on Thoracic and Abdominal Movement Signals of Wearable Piezoelectric Bands. - Yin-Yan Lin; Hau-Tieng Wu; Chi-An Hsu; Po-Chiun Huang; Yuan-Hao Huang; Yu-Lun Lo (IEEE J. Biomed. Health Informatics, 2017)

A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation. - Jhao-Cheng Wu; Chia-Wei Wang; Yuan-Hao Huang; Hau-Tieng Wu; Po-Chiun Huang; Yu-Lun Lo (ISCAS, 2018)

Electromagnetic Energy Harvester Interface Design for Wearable Applications. - Shih-Wei Wang; Yi-Wen Ke; Po-Chiun Huang; Ping-Hsuan Hsieh (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

2 x 3 Arrayed CMOS Capacitive Biosensors for Detection of microRNAs on a Microfluidic System. - Yu-Husan Kuo; Chi-Chien Huang; Yi-Sin Chen; Po-Chiun Huang; Gwo-Bin Lee (NEMS, 2020)

Portable Sleep Apnea Syndrome Screening and Event Detection Using Long Short-Term Memory Recurrent Neural Network. - Hung-Chi Chang; Hau-Tieng Wu; Po-Chiun Huang; Hsi-Pin Ma; Yu-Lun Lo; Yuan-Hao Huang (Sensors, 2020)

A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems. - Yi-Cheng Lin; Ping-Hsuan Hsieh; Jian-Lun Hong; Yu-Hsiang Lai; Jun-Da Chen; Fan-Yi Lin; Yuan-Hao Huang; Po-Chiun Huang (A-SSCC, 2021)

Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). - Jung-Hwan Choi; Po-Chiun Huang; Shouyi Yin; Woogeun Rhee (IEEE J. Solid State Circuits, 2022)

A CMOS Transimpedance Amplifier Accommodating Wide CPD and Input Bias Range for Chaos Lidar. - Hao-Wei Wu; Chung-Yuan Wang; Huan-Jhong Chen; Yi-Cheng Lin; Ping-Hsuan Hsieh; Fan-Yi Lin; Yuan-Hao Huang; Po-Chiun Huang (APCCAS, 2024)