A Predictive Shutdown Technique for GPU Shader Processors. - Po-Han Wang 001; Yen-Ming Chen; Chia-Lin Yang; Yu-Jung Cheng (IEEE Comput. Archit. Lett., 2009)

PM-COSYN: PE and memory co-synthesis for MPSoCs. - Yi-Jung Chen; Chia-Lin Yang; Po-Han Wang 001 (DATE, 2010)

Power gating strategies on GPUs. - Po-Han Wang 001; Chia-Lin Yang; Yen-Ming Chen; Yu-Jung Cheng (ACM Trans. Archit. Code Optim., 2011)

A cycle-level SIMT-GPU simulation framework. - Po-Han Wang 001; Chien-Wei Lo; Chia-Lin Yang; Yu-Jung Cheng (ISPASS, 2012)

Full system simulation framework for integrated CPU/GPU architecture. - Po-Han Wang 001; Gen-Hong Liu; Jen-Chieh Yeh; Tse-Min Chen; Hsu-Yao Huang; Chia-Lin Yang; Shih-Lien Liu; James Greensky (VLSI-DAT, 2014)

Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. - Po-Han Wang 001; Cheng-Hsuan Li; Chia-Lin Yang (DAC, 2016)

Enabling fast preemption via Dual-Kernel support on GPUs. - Li-Wei Shieh; Kun-Chih Chen; Hsueh-Chun Fu; Po-Han Wang 001; Chia-Lin Yang (ASP-DAC, 2017)

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. - Li Wang; Ren-Wei Tsai; Shao-Chung Wang; Kun-Chih Chen; Po-Han Wang 001; Hsiang-Yun Cheng; Yi-Chung Lee; Sheng-Jie Shu; Chun-Chieh Yang; Min-Yih Hsu; Li-Chen Kan; Chao-Lin Lee; et al. (ISPASS, 2017)

Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. - Li-Jhan Chen; Hsiang-Yun Cheng; Po-Han Wang 001; Chia-Lin Yang (IEEE Comput. Archit. Lett., 2017)

Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. - Hsueh-Chun Fu; Po-Han Wang 001; Chia-Lin Yang (DAC, 2018)