A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

Variation-aware and adaptive-latency accesses for reliable low voltage caches. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (VLSI-SoC, 2013)

The reflexive printer: embodying personal memory for social provocation. - Hung-Chi Lee; Wenn-Chieh Tsai; Po-Hao Wang; Rung-Huei Liang; Jane Yung-jen Hsu (Conference on Designing Interactive Systems (Companion Volume), 2014)

The reflexive printer: toward making sense of perceived drawbacks in technology-mediated reminiscence. - Wenn-Chieh Tsai; Po-Hao Wang; Hung-Chi Lee; Rung-Huei Liang; Jane Yung-jen Hsu (Conference on Designing Interactive Systems, 2014)

A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation. - Yung-Hui Yu; Po-Hao Wang; Shang-Jen Tsai; Tien-Fu Chen (VLSI-DAT, 2015)

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. - Po-Hao Wang; Shang-Jen Tsai; Rizal Tanjung; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (Integr., 2016)

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)