A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control. - Sheng-Kai You; Po-Hsuan Chang; Chia-Ming Tsai (SoCC, 2013)

A 10Gb/s 44.2 dB adaptive equalizer with Duobinary tracking loop in 0.18µm CMOS. - Po-Hsuan Chang; An-Siou Li; Chia-Ming Tsai (ISCAS, 2014)

A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS. - Yuanming Zhu; Shengchang Cai; Shiva Kiran; Yang-Hang Fan; Po-Hsuan Chang; Sebastian Hoyos; Samuel Palermo (CICC, 2020)

A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS. - Peng Yan; Chaerin Hong; Po-Hsuan Chang; Hyungryul Kang; Dedeepya Annabattuni; Ankur Kumar; Yang-Hang Fan; Ruida Liu; Ramy Rady; Samuel Palermo (MWSCAS, 2022)

A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit. - Anirban Samanta; Po-Hsuan Chang; Peng Yan; Mingye Fu; Mehmet Berkay On; Ankur Kumar; Hyungryul Kang; Il-Min Yi; Dedeepya Annabattuni; Yu Zhang 099; David Scott; Robert Patti; et al. (OFC, 2023)

A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET. - Po-Hsuan Chang; Anirban Samanta; Peng Yan; Mingye Fu; Yu Zhang 099; Mehmet Berkay On; Ankur Kumar; Hyungryul Kang; Il-Min Yi; Dedeepya Annabattuni; David Scott; Robert Patti; et al. (VLSI Technology and Circuits, 2023)