Design of the multi-channel electroencephalography-based brain-computer interface with novel dry sensors. - Shang-Lin Wu; Lun-De Liao; Chang-Hong Liou; Shi-An Chen; Li-Wei Ko; Bo-Wei Chen; Po-Sheng Wang; Sheng-Fu Chen; Chin-Teng Lin (EMBC, 2012)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)