Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. - Po-Tsang Huang; Wei-Keng Chang; Wei Hwang (APCCAS, 2006)

On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. - Jen-Wei Yang; Po-Tsang Huang; Wei Hwang (APCCAS, 2006)

2-level FIFO architecture design for switch fabrics in network-on-chip. - Po-Tsang Huang; Wei Hwang (ISCAS, 2006)

A 65nm low power 2T1D embedded DRAM with leakage current reduction. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2007)

A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. - Li-Pu Chuang; Ming-Hung Chang; Po-Tsang Huang; Chih-Hao Kan; Wei Hwang (ISCAS, 2008)

"Green" micro-architecture and circuit co-design for ternary content addressable memory. - Po-Tsang Huang; Shu-Wei Chang; Wen-Yen Liu; Wei Hwang (ISCAS, 2008)

Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. - Po-Tsang Huang; Wei-Li Fang; Yin-Ling Wang; Wei Hwang (NOCS, 2008)

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2008)

An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. - Po-Tsang Huang; Wei Hwang (SoCC, 2009)

A decision support system of statistical process control for printed circuit boards manufacturing. - Hsin Rau; Chien-Hung Wu; Wei-Jung Shiang; Po-Tsang Huang (ICMLC, 2010)

Power noise suppression technique using active decoupling capacitor for TSV 3D integration. - Tien-Hung Lin; Po-Tsang Huang; Wei Hwang (SoCC, 2010)

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. - Po-Tsang Huang; Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee; Wei Hwang (J. Low Power Electron., 2010)

On-demand memory sub-system for multi-core SoCs. - Po-Tsang Huang; Yung Chang; Wei Hwang (SoCC, 2011)

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. - Po-Tsang Huang; Wei Hwang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. - Po-Tsang Huang; Wei Hwang (IEEE J. Solid State Circuits, 2011)

Substrate noise suppression technique for power integrity of TSV 3D integration. - Po-Jen Yang; Po-Tsang Huang; Wei Hwang (ISCAS, 2012)

On-chip self-calibrated process-temperature sensor for TSV 3D integration. - Tzu-Ting Chiang; Po-Tsang Huang; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (SoCC, 2012)

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. - Wei-Hung Du; Po-Tsang Huang; Ming-Hung Chang; Wei Hwang (VLSI-DAT, 2012)

Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. - Po-Tsang Huang; Wei Hwang (J. Electr. Comput. Eng., 2012)

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. - Teng-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (BioCAS, 2013)

Through-silicon-via-based double-side integrated microsystem for neural sensing applications. - Chih-Wei Chang; Po-Tsang Huang; Lei-Chun Chou; Shang-Lin Wu; Shih-Wei Lee; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Wei Hwang; Yen-Chi Lee; Chung-Hsi Wu; Kuo-Hua Chen; et al. (ISSCC, 2013)

0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. - Po-Tsang Huang; Shu-Lin Lai; Ching-Te Chuang; Wei Hwang; Jason Huang; Angelo Hu; Paul Kan; Michael Jia; Kimi Lv; Bright Zhang (A-SSCC, 2014)

Energy-efficient configurable discrete wavelet transform for neural sensing applications. - Tang-Hsuan Wang; Po-Tsang Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (ISCAS, 2014)

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. - Po-Tsang Huang; Lei-Chun Chou; Teng-Chieh Huang; Shang-Lin Wu; Tang-Shuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Kuan-Neng Chen; Jin-Chern Chiou; Ching-Te Chuang; Wei Hwang; et al. (ISSCC, 2014)

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. - Chih-Yuan Chang; Po-Tsang Huang; Yi-Chun Chen; Tian-Sheuan Chang; Wei Hwang (SoCC, 2014)

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. - Shang-Lin Wu; Po-Tsang Huang; Teng-Chieh Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2014)

2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. - Po-Tsang Huang; Shang-Lin Wu; Yu-Chieh Huang; Lei-Chun Chou; Teng-Chieh Huang; Tang-Hsuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface. - Wei-Han Cho; Yilei Li; Yanghyo Kim; Po-Tsang Huang; Yuan Du; Sheau Jiung Lee; Mau-Chung Frank Chang (CICC, 2015)

Energy-efficient gas recognition system with event-driven power control. - Chun-Ying Huang; Po-Tsang Huang; Chih-Chao Yang; Ching-Te Chuang; Wei Hwang (SoCC, 2015)

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. - Yi-Ping Kuo; Po-Tsang Huang; Chung-Shiang Wu; Yu-Jie Liang; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (VLSI-DAT, 2015)

Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. - Chih-Chao Yang; Po-Tsang Huang; Chun-Ying Huang; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2015)

The SMEM Seeding Acceleration for DNA Sequence Alignment. - Mau-Chung Frank Chang; Yu-Ting Chen 003; Jason Cong; Po-Tsang Huang; Chun-Liang Kuo; Cody Hao Yu (FCCM, 2016)

An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (ISCAS, 2016)

10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. - Wei-Han Cho; Yilei Li; Yuan Du; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Sheau Jiung Lee; Huan-Neng Ron Chen; Chewnpu Jou; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2016)

Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. - Ming Chen; Po-Tsang Huang; Shang-Lin Wu; Wei Hwang; Ching-Te Chuang (SoCC, 2016)

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. - Yuan Du; Wei-Han Cho; Yilei Li; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Yanghyo Kim; Zuow-Zun Chen; Sheau Jiung Lee; Mau-Chung Frank Chang (VLSI Circuits, 2016)

Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. - Chia-Ning Chang; Yin-Nien Chen; Po-Tsang Huang; Pin Su; Ching-Te Chuang (ISCAS, 2017)

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. - Po-Tsang Huang; Yu-Chieh Huang; Shang-Lin Wu; Yu-Chen Hu; Ming-Wei Lu; Ting-Wei Sheng; Fung-Kai Chang; Chun-Pin Lin; Nien-Shang Chang; Hung-Lieh Chen; Chi-Shi Chen; Jeng-Ren Duann; et al. (ISCAS, 2017)

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection. - Yuan Du; Wei-Han Cho; Po-Tsang Huang; Yilei Li; Chien-Heng Wong; Jieqiong Du; Yanghyo Kim; Boyu Hu; Li Du; Chun-Chen Liu; Sheau Jiung Lee; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2017)

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (IEEE Trans. Biomed. Circuits Syst., 2017)

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. - Shang-Lin Wu; Kuang-Yu Li; Po-Tsang Huang; Wei Hwang; Ming-Hsien Tu; Sheng-Chi Lung; Wei-Sheng Peng; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. - Jason Cong; Licheng Guo; Po-Tsang Huang; Peng Wei 004; Tianhe Yu (FCCM, 2018)

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. - Jason Cong; Licheng Guo; Po-Tsang Huang; Peng Wei 004; Tianhe Yu (FPL, 2018)

0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. - Yun-Sheng Chan; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (SoCC, 2018)

28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. - Yi-Chun Wu; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (VLSI-DAT, 2018)

An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. - I-Chen Wu; Po-Tsang Huang; Chin-Yang Lo; Wei Hwang (AICAS, 2019)

A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. - Jieqiong Du; Chien-Heng Wong; Yo-Hao Tu; Wei-Han Cho; Yilei Li; Yuan Du; Po-Tsang Huang; Sheau Jiung Lee; Mau-Chung Frank Chang (NOCS, 2019)

28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. - Huan-Jan Tseng; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (SoCC, 2019)

Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration. - Shu-Feng Cheng; Po-Tsang Huang; Li-Chun Wang 001; Mau-Chung Frank Chang (IEEE Des. Test, 2019)

Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. - Chin-Yang Lo; Po-Tsang Huang; Wei Hwang (AICAS, 2020)

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. - Po-Tsang Huang; Tzung-Han Tsai; Po-Jen Yang; Wei Hwang; Hung-Ming Chen (SoCC, 2020)

3D On-Demand Flying Mobile Communication for Millimeter-Wave Heterogeneous Networks. - Kai-Ten Feng; Li-Hsiang Shen; Chi-Yu Li 001; Po-Tsang Huang; Sau-Hsuan Wu; Li-Chun Wang 001; Yi-Bing Lin; Mau-Chung Frank Chang (IEEE Netw., 2020)

Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory. - Sunanda Thunder; Parthasarathi Pal; Yeong-Her Wang; Po-Tsang Huang (ICICDT, 2021)

An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. - Po-Tsang Huang; Ting-Wei Liu; Wei Lu; Yu-Hsien Lin; Wei Hwang (ISOCC, 2021)

An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. - Wei Lu; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. - Po-Tsang Huang; I-Chen Wu; Chin-Yang Lo; Wei Hwang (IEEE Open J. Circuits Syst., 2021)

Design and Implementation for Deep Learning Based Adjustable Beamforming Training for Millimeter Wave Communication Systems. - Li-Hsiang Shen; Ting-Wei Chang; Kai-Ten Feng; Po-Tsang Huang (IEEE Trans. Veh. Technol., 2021)

Rotational motion-aware beam refinement for high-throughput mmWave communications. - Tourangbam Harishore Singh; Shabirahmed Badashasab Jigalur; Po-Tsang Huang (Wirel. Networks, 2021)

Design Exploration of An Energy-Efficient Acceleration System for CNNs on Low-Cost Resource-Constraint SoC-FPGAs. - Shao-Cheng Wen; Po-Tsang Huang (AICAS, 2022)

Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications. - Yannick Raffel; Sunanda Thunder; Maximilian Lederer; Ricardo Olivo; Raik Hoffmann; Luca Pirro; Sven Beyer; Talha Chohan; Po-Tsang Huang; Sourav De 002; Thomas Kämpfe; Konrad Seidel; et al. (ICICDT, 2022)

Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator. - Jui-I Kao; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (ISOCC, 2022)

Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. - Wei Lu; Pei-Yu Ge; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (ISOCC, 2022)

Cognitive Bus Coding Scheme for Inter-Chip Communications of Deep Learning Accelerator Chiplet on Low-cost Si and Glass Interposer. - Yu-Hong Chang; Tourangbam Harishore Singh; Po-Tsang Huang (MCSoC, 2022)

Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks. - Yun-Ru Yang; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (MCSoC, 2022)

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. - Jie Zhang; Wei Lu; Po-Tsang Huang; Sih-Han Li; Tsung-Yi Hung; Shih-Hsien Wu; Ming-Ji Dai; I-Shan Chung; Wen-Chao Chen; Chin-Hung Wang; Shyh-Shyuan Sheu; Hung-Ming Chen; et al. (VLSI Technology and Circuits, 2022)

Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core. - Sunanda Thunder; Po-Tsang Huang (CoRR, 2022)

Digi-FH-OFDM: An all-digital wideband frequency-hopped OFDM system. - Amit Sravan Bora; Tourangbam Harishore Singh; Po-Tsang Huang (Phys. Commun., 2022)

Reshaping System Design in 3D Integration: Perspectives and Challenges. - Hung-Ming Chen; Chu-Wen Ho; Shih-Hsien Wu; Wei Lu; Po-Tsang Huang; Hao-Ju Chang; Chien-Nan Jimmy Liu (ISPD, 2023)

On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC. - Po-Yang Chen; Chang-Yun Liu; Hung-Ming Chen; Po-Tsang Huang (ISQED, 2023)

A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block. - Cheng-Chen Lin; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (AICAS, 2024)

Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits. - Ting-An Lin; Po-Tsang Huang (APCCAS, 2024)

A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. - Wei Lu; Han-Hsiang Pei; Jheng-Rong Yu; Hung-Ming Chen; Po-Tsang Huang (ISCAS, 2024)

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. - Wei Lu; Jie Zhang; Yi-Hui Wei; Hsu-Ming Hsiao; Sih-Han Li; Chao-Kai Hsu; Chih-Cheng Hsiao; Feng-Hsiang Lo; Shyh-Shyuan Sheu; Chin-Hung Wang; Wei-Chung Lo; Shih-Chieh Chang; et al. (VLSI Technology and Circuits, 2024)

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. - Bo-Jheng Shih; Yu-Ming Pan; Hao-Tung Chung; Chieh-Ling Lee; I-Chun Hsieh; Nein-Chih Lin; Chih-Chao Yang; Po-Tsang Huang; Hung-Ming Chen; Chiao-Yen Wang; Huan-Yu Chiu; Huang-Chung Cheng; et al. (VLSI Technology and Circuits, 2024)

Energy-Efficient Sparse FFT and Compressed Transpose Memory for mmWave FMCW Radar Sensor System. - Tourangbam Harishore Singh; Po-Tsang Huang; Kung-Shuo Kao; Chih-Shiang Cheng; Kuei-Ann Wen; Lichun Wang 001 (IEEE Trans. Instrum. Meas., 2024)

Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator. - Liang-Te Huang; Wei Lu; Hung-Ming Chen; Po-Tsang Huang (ISCAS, 2025)