A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. - Po-Wei Chiu; Muqing Liu; Qianying Tang; Chris H. Kim (A-SSCC, 2018)

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. - Po-Wei Chiu; Somnath Kundu; Qianying Tang; Chris H. Kim (IEEE J. Solid State Circuits, 2018)

A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. - Gyusung Park; Minsu Kim; Nakul Pande; Po-Wei Chiu; Jeehwan Song; Chris H. Kim (CICC, 2019)

22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. - Po-Wei Chiu; Chris H. Kim (ISSCC, 2020)

A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. - Ibrahim Ahmed 002; Po-Wei Chiu; Chris H. Kim (VLSI Circuits, 2020)

A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. - Ibrahim Ahmed 002; Po-Wei Chiu; William Moy; Chris H. Kim (IEEE J. Solid State Circuits, 2021)

A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. - Po-Wei Chiu; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Integrating RC6 Stream Cipher to A Chaotic Synchronization System. - Feng-Hsiag Hsiao; Po-Wei Chiu; Shou-Wen Chang (SmartCloud, 2023)