Buffer design and optimization for lut-based structured ASIC design styles. - Po-Yang Hsu; Shu-Ting Lee; Fu-Wei Chen; Yi-Yu Liu (ACM Great Lakes Symposium on VLSI, 2009)

Stacking signal TSV for thermal dissipation in global routing for 3D IC. - Po-Yang Hsu; Hsien-Te Chen; TingTing Hwang (ASP-DAC, 2013)

Thread-criticality aware dynamic cache reconfiguration in multi-core system. - Po-Yang Hsu; TingTing Hwang (ICCAD, 2013)

Routability optimization for crossbar-switch structured ASIC design. - Mei-Hsiang Tsai; Po-Yang Hsu; Hung-Yi Li; Yi-Huang Hung; Yi-Yu Liu (ACM Trans. Design Autom. Electr. Syst., 2013)

Compaction-free compressed cache for high performance multi-core system. - Po-Yang Hsu; Pei-Lan Lin; TingTing Hwang (ICCAD, 2014)

Hybrid LUT and SOP Reconfigurable Architecture. - Po-Yang Hsu; Yung-Chih Chen; Yi-Yu Liu (J. Inf. Sci. Eng., 2014)

Buffer Design and Assignment for Structured ASIC. - Po-Yang Hsu; Yi-Yu Liu (J. Inf. Sci. Eng., 2014)

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. - Po-Yang Hsu; Hsien-Te Chen; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Reducing the Standby Power Consumption of the S3 State for PCs. - Te Huang; Ying-Wen Bai; Po-Yang Hsu (IEICE Trans. Electron., 2015)

A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. - HsinChen Chen; Rolf Lagerquist; Ashish Nayak; Hugh Mair; Gokulakrishnan Manoharan; Ericbill Wang; Gordon Gammie; Efron Ho; Anand Rajagopalan; Lee-Kee Yong; Ramu Madhavaram; Madhur Jagota; et al. (ISSCC, 2021)