Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. - Harry H. Chen; Simon Y.-H. Chen; Po-Yao Chuang; Cheng-Wen Wu (ATS, 2016)

Cell-aware test generation time reduction by using switch-level ATPG. - Po-Yao Chuang; Cheng-Wen Wu; Harry H. Chen (ITC-Asia, 2017)

Covering hard-to-detect defects by thermal quorum sensing. - Po-Yao Chuang; Cheng-Wen Wu; Harry H. Chen (ETS, 2018)

A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. - Po-Yao Chuang; Pai-Yu Tan; Cheng-Wen Wu; Juin-Ming Lu (DAC, 2020)

A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. - Pai-Yu Tan; Po-Yao Chuang; Yen-Ting Lin; Cheng-Wen Wu; Juin-Ming Lu (CoRR, 2020)

A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. - Hong-Hao Wang; Po-Yao Chuang; Cheng-Wen Wu (VLSI-DAT, 2022)

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Slimane Boutobza; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (3DIC, 2023)

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. - Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen (ITC-Asia, 2023)

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (VTS, 2023)

New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. - Erik Jan Marinissen; Adrian Evans; Po-Yao Chuang; Martin Keim; Anshuman Chandra (ETS, 2024)

Test and Repair Improvements for UCIe. - Tsung-Hsuan Wang; Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen (ETS, 2024)

IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. - Erik Jan Marinissen; Vineet Pancholi; Po-Yao Chuang; Martin Keim (VTS, 2024)

Extendable E2I-TEST for Chiplet-based Inter-die Interconnects. - Po-Yao Chuang; Erik Jan Marinissen (ETS, 2025)

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. - Po-Yao Chuang; Francesco Lorenzelli; Cheng-Wen Wu; Erik Jan Marinissen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)