ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. - Yuan-Wen Hsiao; Ming-Dou Ker; Po-Yen Chiu; Chun Huang; Yuh-Kuang Tseng (SoCC, 2007)

On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. - Ming-Dou Ker; Po-Yen Chiu; Fu-Yi Tsai; Yeong-Jar Chang (ISCAS, 2009)

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. - Po-Yen Chiu; Ming-Dou Ker (SoCC, 2013)

Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices. - Ming-Dou Ker; Po-Yen Chiu (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. - Po-Yen Chiu; Ming-Dou Ker (Microelectron. Reliab., 2014)