Scalable and bijective cells for C-testable iterative logic array architectures. - Bo-Yuan Ye; Po-Yu Yeh; Sy-Yen Kuo; Ing-Yi Chen (IET Circuits Devices Syst., 2009)

Design-for-testability techniques for CORDIC design. - Bo-Yuan Ye; Po-Yu Yeh; Sy-Yen Kuo; Ing-Yi Chen (Microelectron. J., 2009)

Effective design-for-testability techniques for H.264 all-binary integer motion estimation. - Po-Yu Yeh; Bo-Yuan Ye; Sy-Yen Kuo; Ing-Yi Chen (IET Circuits Devices Syst., 2010)

23.5 MAE: A 3nm 0.168mm2 576MAC Mini AutoEncoder with Line-Based Depth-First Scheduling for Generative AI in Vision on Edge Devices. - Shih-Wei Hsieh; Chia-Hung Yuan; Ming-Hung Lin; Ping-Yuan Tsai; You-Yu Nian; Chia-Yuan Cheng; Hung-Wei Chih; Po-Han Chiang; Ming-Hsuan Chiang; Yuan-Jung Kuo; Yu-Wei Wu; Yi-Syuan Chen; et al. (ISSCC, 2025)