Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. - Wen-mei W. Hwu; Pohua P. Chang (ISCA, 1988)

Trace selection for compiling large C application programs to microcode. - Pohua P. Chang; Wen-mei W. Hwu (MICRO, 1988)

Control flow optimization for supercomputer scalar processing. - Pohua P. Chang; Wen-mei W. Hwu (ICS, 1989)

Achieving High Instruction Cache Performance with an Optimizing Compiler. - Wen-mei W. Hwu; Pohua P. Chang (ISCA, 1989)

Comparing Software and Hardware Schemes For Reducing the Cost of Branches. - Wen-mei W. Hwu; Thomas M. Conte; Pohua P. Chang (ISCA, 1989)

Inline Function Expansion for Compiling C Programs. - Wen-mei W. Hwu; Pohua P. Chang (PLDI, 1989)

The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. - Scott A. Mahlke; Nancy J. Warter; William Y. Chen; Pohua P. Chang; Wen-mei W. Hwu (ICPP (2), 1991)

Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. - Pohua P. Chang; William Y. Chen; Scott A. Mahlke; Wen-mei W. Hwu (MICRO, 1991)

Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. - William Y. Chen; Scott A. Mahlke; Pohua P. Chang; Wen-mei W. Hwu (MICRO, 1991)

Using Profile Information to Assist Classic Code Optimizations. - Pohua P. Chang; Scott A. Mahlke; Wen-mei W. Hwu (Softw. Pract. Exp., 1991)

Tolerating data access latency with register preloading. - William Y. Chen; Scott A. Mahlke; Wen-mei W. Hwu; Tokuzo Kiyohara; Pohua P. Chang (ICS, 1992)

Profile-guided Automatic Inline Expansion for C Programs. - Pohua P. Chang; Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu (Softw. Pract. Exp., 1992)

Efficient Instruction Sequencing with Inline Target Insertion. - Wen-mei W. Hwu; Pohua P. Chang (IEEE Trans. Computers, 1992)

The Effect of Code Expanding Optimizations on Instruction Cache Design. - William Y. Chen; Pohua P. Chang; Thomas M. Conte; Wen-mei W. Hwu (IEEE Trans. Computers, 1993)

The superblock: An effective technique for VLIW and superscalar compilation. - Wen-mei W. Hwu; Scott A. Mahlke; William Y. Chen; Pohua P. Chang; Nancy J. Warter; Roger A. Bringmann; Roland G. Ouellette; Richard E. Hank; Tokuzo Kiyohara; Grant E. Haab; John G. Holm; Daniel M. Lavery (J. Supercomput., 1993)

Introduction. - Pohua P. Chang (HICSS (1), 1994)

Profile-Guided Multi-Heuristic Branch Prediction. - Pohua P. Chang; Utpal Banerjee (ICPP (1), 1995)

Integer Loop Code Generation for VLIW. - James Radigan; Pohua P. Chang; Utpal Banerjee (LCPC, 1995)

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. - Pohua P. Chang; Daniel M. Lavery; Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu (IEEE Trans. Computers, 1995)

Three Architecutral Models for Compiler-Controlled Speculative Execution. - Pohua P. Chang; Nancy J. Warter; Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu (IEEE Trans. Computers, 1995)

Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism. - David A. Berson; Pohua P. Chang; Rajiv Gupta 001; Mary Lou Soffa (LCPC, 1996)

Bidirectional Scheduling: A New Global Code Scheduling Approach. - Pohua P. Chang; Dong-yuan Chen; Yong-Fong Lee; Youfeng Wu; Utpal Banerjee (LCPC, 1996)

Memory Optimizations in the Intel Reference Compiler. - K. Sridharan 002; Pohua P. Chang; Utpal Banerjee; Ravi Narayanaswamy; Suresh Rao (LCPC, 1996)

Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution. - Po-Yung Chang; Eric Hao; Yale N. Patt; Pohua P. Chang (Int. J. Parallel Program., 1996)

IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. - Pohua P. Chang; Scott A. Mahlke; William Y. Chen; Nancy J. Warter; Wen-mei W. Hwu (25 Years ISCA: Retrospectives and Reprints, 1998)