Industrial experimentation of high-level synthesis. - Polen Kission; Etienne Closse; Laurent Bergher; Ahmed Amine Jerraya (EURO-DAC, 1993)

Structured Design Methodology for High-Level Design. - Polen Kission; Hong Ding; Ahmed Amine Jerraya (DAC, 1994)

Accelerating the design process by using architectural synthesis. - Polen Kission; Hong Ding; Ahmed Amine Jerraya (RSP, 1994)

VHDL based design methodology for hierarchy and component re-use. - Polen Kission; Hong Ding; Ahmed Amine Jerraya (EURO-DAC, 1995)

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. - Elisabeth Berrebi; Polen Kission; Serge Vernalde; S. De Troch; Jean-Claude Herluison; Jean Fréhel; Ahmed Amine Jerraya; Ivo Bolsens (DAC, 1996)

Analysis of different protocol description styles in VHDL for high-level synthesis. - Maher Rahmouni; Ahmed Amine Jerraya; Polen Kission; Antonio Carneiro de Mesquita Filho; Aloysio Pedroza; Luci Pirmez (EURO-DAC, 1996)

Embedded architectural simulation within behavioral synthesis environment. - Abderrazek Jemai; Polen Kission; Ahmed Amine Jerraya (ASP-DAC, 1997)

Architectural Simulation in the Context of Behavioral Synthesis. - Abderrazek Jemai; Polen Kission; Ahmed Amine Jerraya (DATE, 1998)

The application of high-level synthesis techniques for the generation of pipelined reprogrammable microcontrollers. - Mohamed Benmohammed; Abdelatif Rahmoune; Polen Kission (ICECS, 2000)