A high-speed low-power JFET pull-down ECL circuit. - Hyun J. Shin; Pong-Fei Lu; Ching-Te Chuang (IEEE J. Solid State Circuits, 1991)

High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. - Ching-Te Chuang; Kenneth Chin; Hyun J. Shin; Pong-Fei Lu (IEEE J. Solid State Circuits, 1992)

High-speed low-power Darlington ECL circuit. - Ching-Te Chuang; Kenneth Chin; Pong-Fei Lu; Hyun J. Shin (IEEE J. Solid State Circuits, 1993)

Floating body effects in partially-depleted SOI CMOS circuits. - Pong-Fei Lu; Jin Ji; Ching-Te Chuang; Lawrence F. Wagner; Chang-Ming Hsieh; Jente Benedict Kuang; L. Hsu; Mario M. Pelella Jr.; Shao-Fu Sanford Chu; Carl J. Anderson (ISLPED, 1996)

Floating-body effects in partially depleted SOI CMOS circuits. - Pong-Fei Lu; Ching-Te Chuang; Jin Ji; Lawrence F. Wagner; Chang-Ming Hsieh; Jente B. Kuang; Louis Lu-Chen Hsu; Mario M. Pelella Jr.; Shao-Fu Sanford Chu; Carl J. Anderson (IEEE J. Solid State Circuits, 1997)

SOI for digital CMOS VLSI: design considerations and advances. - Ching-Te Chuang; Pong-Fei Lu; Carl J. Anderson (Proc. IEEE, 1998)

A Semi-Custom Design Flow in High-Performance Microprocessor Design. - Gregory A. Northrop; Pong-Fei Lu (DAC, 2001)

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. - Pong-Fei Lu; Nianzheng Cao; Leon J. Sigal; Pieter Woltgens; Raphael Robertazzi; David F. Heidel (ISLPED, 2006)

Design of ring oscillator structures for measuring isolated NBTI and PBTI. - Tony T. Kim; Pong-Fei Lu; Chris H. Kim (ISCAS, 2012)

On-chip circuit to monitor long-term NBTI and PBTI degradation. - Keith A. Jenkins; Pong-Fei Lu (Microelectron. Reliab., 2013)

Row Based Dual-VDD Island Generation and Placement. - Hua Xiang 001; Haifeng Qian; Ching Zhou; Yu-Shiang Lin; Fanchieh Yee; Andrew Sullivan; Pong-Fei Lu (DAC, 2014)

Long-term NBTI degradation under real-use conditions in IBM microprocessors. - Pong-Fei Lu; Keith A. Jenkins; Tobias Webel; Oliver Marquardt; Birgit Schubert (Microelectron. Reliab., 2014)

Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology. - Pong-Fei Lu; Keith A. Jenkins; K. Paul Muller; Ralf Schaufler (IRPS, 2015)

A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology. - Tony Tae-Hyoung Kim; Pong-Fei Lu; Keith A. Jenkins; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Synthesis design strategies for energy-efficient microprocessors. - Ching Zhou; Yu-Shiang Lin; Pong-Fei Lu; Bruce M. Fleischer; David J. Frank; Leland Chang (ICCD, 2016)

Gate movement for timing improvement on row based Dual-VDD designs. - Hua Xiang 001; Lakshmi N. Reddy; Haifeng Qian; Ching Zhou; Yu-Shiang Lin; Fanchieh Yee; Andrew Sullivan; Pong-Fei Lu (ISQED, 2016)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)