Compression architecture for bit-write reduction in non-volatile memory technologies. - David B. Dgien; Poovaiah M. Palangappa; Nathan Altay Hunter; Jiayin Li; Kartik Mohanram (NANOARCH, 2014)

Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories. - Poovaiah M. Palangappa; Kartik Mohanram (ACM Great Lakes Symposium on VLSI, 2015)

CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. - Poovaiah M. Palangappa; Kartik Mohanram (HPCA, 2016)

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory. - Poovaiah M. Palangappa; Jiayin Li; Kartik Mohanram (IEEE Trans. Computers, 2016)

CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs. - Poovaiah M. Palangappa; Kartik Mohanram (ACM Trans. Archit. Code Optim., 2017)

ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories. - Shivam Swami; Poovaiah M. Palangappa; Kartik Mohanram (ACM Trans. Archit. Code Optim., 2017)

CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. - Poovaiah M. Palangappa; Kartik Mohanram (DAC, 2018)

RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs. - Poovaiah M. Palangappa; Kartik Mohanram (ICCAD, 2018)

Combating Bit Errors From Stuck Cells in Flash Memory Using Novel Information Theory Techniques. - Ravi Motwani; Zion S. Kwok; Poovaiah M. Palangappa (ICNC, 2018)

Graph Enhanced Feature Engineering for Privacy Preserving Recommendation Systems. - Chendi Xue; Xinyao Wang; Yu Zhou; Poovaiah M. Palangappa; Rita Brugarolas Brufau; Aasavari Dhananjay Kakne; Ravi Motwani; Ke Ding; Jian Zhang (RecSys Challenge, 2023)