A fractional delay-locked loop for on chip clock generation applications. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ASP-DAC, 2005)

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (3), 2005)

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (5), 2005)

Behavioral modeling of clock feed-through and channel charge injection non-ideal effects in SIMULINK for switched-capacitor integrator. - Pooya Torkzadeh; Seyed Mojtaba Atarodi (Simul. Model. Pract. Theory, 2010)

Design trade-offs of a capacitance-to-voltage converter with a zoom-in technique for grounded capacitive sensors. - Arash Ahmadpour Bijargah; Ali Heidary; Pooya Torkzadeh; Stoyan N. Nihtianov (Int. J. Circuit Theory Appl., 2018)

An accurate and power-efficient period-modulator-based interface for grounded capacitive sensors. - Arash Ahmadpour Bijargah; Ali Heidary; Pooya Torkzadeh; Stoyan N. Nihtianov (Int. J. Circuit Theory Appl., 2019)

A study of analog decision feedback equalization for ADC-Based serial link receivers. - Azad Mahmoudi; Pooya Torkzadeh; Massoud Dousti (Integr., 2019)

A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects. - Hossein Sariri; Pooya Torkzadeh; Sirus Sadughi (Integr., 2019)

A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology. - Siavash Heydarzadeh; Pooya Torkzadeh; Sirus Sadughi (Microelectron. J., 2019)

Modification and hardware implementation of cortex-like object recognition model. - Alireza Mohammadi Anbaran; Pooya Torkzadeh; Reza Ebrahimpour; Nasour Bagheri (IET Image Process., 2020)

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications. - Sahel Javahernia; Esmaeil Najafi Aghdam; Pooya Torkzadeh (J. Circuits Syst. Comput., 2020)

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC-DC Converter for Implantable Devices. - Najmeh Cheraghi Shirazi; Abumoslem Jannesari; Pooya Torkzadeh (J. Circuits Syst. Comput., 2020)

Designing a Low-Power LNA and Filter for Portable EEG Acquisition Applications. - Marzieh Moradi; Massoud Dousti; Pooya Torkzadeh (IEEE Access, 2021)

A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications. - Azad Mahmoudi; Pooya Torkzadeh; Massoud Dousti (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration. - Farshad Aghasharif; Mohammadreza Malekpour; Reza Bigdeli; Pooya Torkzadeh (Integr., 2022)

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits. - Hamideh Khajehnasir-Jahromi; Pooya Torkzadeh; Massoud Dousti (Frontiers Inf. Technol. Electron. Eng., 2022)

A 256 × 256 CMOS image sensor with differential readout and data converter circuits. - Khadijeh Karamzadeh; Masood Teymouri; Massoud Dousti; Pooya Torkzadeh (Int. J. Circuit Theory Appl., 2023)

A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter. - Abolfazl Roshanpanah; Pooya Torkzadeh; Khosrow Hajsadeghi; Massoud Dousti (J. Circuits Syst. Comput., 2024)

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance. - Seyed Arman Sabaghpour; Behzad Ebrahimi; Pooya Torkzadeh (Integr., 2025)

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA. - Abolfazl Roshanpanah; Pooya Torkzadeh; Khosrow Hajsadeghi; Massoud Dousti (Circuits Syst. Signal Process., 2025)