Design and implementation of real time video processor. - Shishpal Rawat; Poras T. Balsara; Mary Jane Irwin; Tom Mackowiak (ICASSP, 1986)

Systolic & semi-systolic digit serial multipliers. - Poras T. Balsara; Robert Michael Owens (IEEE Symposium on Computer Arithmetic, 1987)

Digit Serial Multipliers. - Poras T. Balsara; Robert Michael Owens; Mary Jane Irwin (J. Parallel Distributed Comput., 1991)

Image processing on a memory array architecture. - Poras T. Balsara; Mary Jane Irwin (J. VLSI Signal Process., 1991)

Design and implementation of a multi-microprocessor architecture for image processing. - Arun Vaidyanathan; Eric M. Dowling; Poras T. Balsara (Microprocess. Microsystems, 1992)

Intermediate-level vision tasks on a memory array architecture. - Poras T. Balsara; Mary Jane Irwin (Mach. Vis. Appl., 1992)

Energy optimization of multi-level processor cache architectures. - Uming Ko; Poras T. Balsara; Ashwini K. Nanda (ISLPD, 1995)

Hierarchy embedded differential image for progressive transmission using lossless compression. - Whoi-Yul Kim; Poras T. Balsara; David T. Harper III; Jon Wong Park (IEEE Trans. Circuits Syst. Video Technol., 1995)

An architecture for a DSP field-programmable gate array. - M. Agarwala; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Short-circuit power driven gate sizing technique for reducing power dissipation. - Uming Ko; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Design techniques for high performance, energy efficient control logic. - Uming Ko; Anthony M. Hill; Poras T. Balsara (ISLPED, 1996)

Leap frog multiplier. - Shivaling S. Mahant-Shetti; Carl Lemonds; Poras T. Balsara (ISLPED, 1996)

Performance of CMOS differential circuits. - Pius Ng; Poras T. Balsara; Don Steiss (IEEE J. Solid State Circuits, 1996)

LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. - Sharat Prasad; Kamran Kiasaleh; Poras T. Balsara (INFOCOM, 1998)

Energy optimization of multilevel cache architectures for RISC and CISC processors. - Uming Ko; Poras T. Balsara; Ashwini K. Nanda (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. - Nagaraj Ns; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 1999)

High performance low power array multiplier using temporal tiling. - Shivaling S. Mahant-Shetti; Poras T. Balsara; Carl Lemonds (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Reconfigurable Array Media Processor (RAMP). - Kamlesh Rath; Sirisha Tangirala; Patrick Friel; Poras T. Balsara; Jose Flores; John P. Wadley (FCCM, 2000)

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. - Khurram Muhammad; Robert Bogdan Staszewski; Poras T. Balsara (ISLPED, 2000)

A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. - Robert Bogdan Staszewski; Khurram Muhammad; Poras T. Balsara (IEEE J. Solid State Circuits, 2000)

High-performance energy-efficient D-flip-flop circuits. - Uming Ko; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Challenges in integrated CMOS transceivers for short distance wireless. - Khurram Muhammad; Robert Bogdan Staszewski; Poras T. Balsara (ACM Great Lakes Symposium on VLSI, 2001)

Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. - Nagaraj Ns; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 2001)

Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. - Khurram Muhammad; Robert Bogdan Staszewski; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. - N. S. Nagaraj; Poras T. Balsara; Cyrus D. Cantrell (ASP-DAC/VLSI Design, 2002)

Benchmarks for Interconnect Parasitic Resistance and Capacitance. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Frank Cano; Usha Narasimha; Mak Kulkarni; Poras T. Balsara; Cyrus D. Cantrell (ISQED, 2003)

Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation. - Robert Bogdan Staszewski; Dirk Leipold; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process. - Robert Bogdan Staszewski; Dirk Leipold; Khurram Muhammad; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. - Mohammad J. Akhbarizadeh; Mehrdad Nourani; Deepak S. Vijayasarathi; Poras T. Balsara (ICCD, 2004)

Event-driven simulation and modeling of an RF oscillator. - Robert Bogdan Staszewski; Chan Fernando; Poras T. Balsara (ISCAS (4), 2004)

Interconnect Modeling for Copper/Low-k Technologies. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Roger Griesmer; Poras T. Balsara (VLSI Design, 2004)

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. - Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; et al. (IEEE J. Solid State Circuits, 2004)

Exploiting temporal idleness to reduce leakage power in programmable architectures. - Rajarshee P. Bharadwaj; Rajan Konar; Poras T. Balsara; Dinesh Bhatia (ASP-DAC, 2005)

FPGA Architecture for Standby Power Management. - Rajarshee P. Bharadwaj; Rajan Konar; Dinesh Bhatia; Poras T. Balsara (FPT, 2005)

Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. - Deepak S. Vijayasarathi; Mehrdad Nourani; Mohammad J. Akhbarizadeh; Poras T. Balsara (ICCD, 2005)

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. - Mukesh Chugh; Dinesh Bhatia; Poras T. Balsara (IPDPS, 2005)

VHDL Simulation and Modeling of an All-Digital RF Transmitter. - Robert Bogdan Staszewski; Roman Staszewski; Poras T. Balsara (IWSOC, 2005)

The Impact of Inductance on Transients Affecting Gate Oxide Reliability. - N. S. Nagaraj; William R. Hunter; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 2005)

Power Switch Network Design for MTCMOS. - Ramaprasath Vilangudipitchai; Poras T. Balsara (VLSI Design, 2005)

Phase-domain all-digital phase-locked loop. - Robert Bogdan Staszewski; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Event-driven Simulation and modeling of phase noise of an RF oscillator. - Robert Bogdan Staszewski; Chan Fernando; Poras T. Balsara (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination. - Robert Bogdan Staszewski; Dirk Leipold; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

SoC with an integrated DSP and a 2.4-GHz RF transmitter. - Robert Bogdan Staszewski; Roman Staszewski; John L. Wallberg; Tom Jung; Chih-Ming Hung; Jinseok Koh; Dirk Leipold; Kenneth Maggio; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Generic Network Interfaces for Plug and Play NoC Based Architecture. - Sanjay Pratap Singh; Shilpa Bhoj; Dheera Balasubramanian; Tanvi Nagda; Dinesh Bhatia; Poras T. Balsara (ARC, 2006)

Reconfigurable CAM Architecture for Network Search Engines. - Mehrdad Nourani; Deepak S. Vijayasarathi; Poras T. Balsara (ICCD, 2006)

A generalized signal reconstruction method for designing interpolation filters. - Ioannis L. Syllaios; Poras T. Balsara; Oren E. Eliezer (ISCAS, 2006)

Exploring Logic Block Granularity in Leakage Tolerant FPGA. - Rajan Konar; Rajarshee P. Bharadwaj; Dinesh Bhatia; Poras T. Balsara (VLSI Design, 2006)

A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. - V. Ramakrishnan; Poras T. Balsara (VLSI Design, 2006)

I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process. - Imtinan Elahi; Khurram Muhammad; Poras T. Balsara (IEEE J. Solid State Circuits, 2006)

IIP2 and DC Offsets in the Presence of Leakage at LO Frequency. - Imtinan Elahi; Khurram Muhammad; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. - Robert Bogdan Staszewski; Sudheer K. Vemulapalli; Prasant Vallur; John L. Wallberg; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications. - Ioannis L. Syllaios; Poras T. Balsara; Robert Bogdan Staszewski (CICC, 2007)

A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. - Viral K. Parikh; Poras T. Balsara; Oren E. Eliezer; Jaimin Mehta (ISCAS, 2007)

A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. - Viral K. Parikh; Poras T. Balsara; Oren E. Eliezer; Jaimin Mehta (ISCAS, 2007)

Effect of Word-length Precision on the Performance of MIMO Systems. - Chitranjan K. Singh; Naofal Al-Dhahir; Poras T. Balsara (ISCAS, 2007)

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios. - Ioannis L. Syllaios; Poras T. Balsara; Robert Bogdan Staszewski (PIMRC, 2007)

VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. - Chitranjan K. Singh; Sushma Honnavara Prasad; Poras T. Balsara (VLSI Design, 2007)

Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. - Raghunath Cherukuri; Poras T. Balsara (VTC Fall, 2007)

All-Digital PLL With Ultra Fast Settling. - Robert Bogdan Staszewski; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Time-Domain Modeling of an RF All-Digital PLL. - Ioannis L. Syllaios; Robert Bogdan Staszewski; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers. - Oren Eytan Eliezer; Robert Bogdan Staszewski; Imran Bashir; Sumeer Bhatara; Poras T. Balsara (IEEE J. Solid State Circuits, 2009)

Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation. - Imtinan Elahi; Khurram Muhammad; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters. - Viral K. Parikh; Poras T. Balsara; Oren E. Eliezer (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. - Mangesh K. Kunchamwar; Durga P. Prasad; Pawan Hegde; Poras T. Balsara; Rama Sangireddy (ICPP Workshops, 2010)

Design of a link-controller architecture for multiple serial link protocols. - Lei Wang; Pawankumar Hegde; Vishal Nawathe; Roman Staszewski; Poras T. Balsara; Vojin G. Oklobdzija (SoCC, 2010)

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. - Jaimin Mehta; Vasile Zoicas; Oren E. Eliezer; Robert Bogdan Staszewski; Sameh Rezeq; Mitch Entezari; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters. - Ioannis L. Syllaios; Poras T. Balsara; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder. - Venkata K. Kidambi Srinivasan; Chitranjan K. Singh; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Multi-clock domain analysis and modeling of all-digital frequency synthesizers. - Ioannis L. Syllaios; Poras T. Balsara (ISCAS, 2011)

Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop. - Ramakrishnan Venkatasubramanian; Sujan K. Manohar; Poras T. Balsara (NANOARCH, 2011)

A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. - Imran Bashir; Robert Bogdan Staszewski; Oren E. Eliezer; Bhaskar Banerjee; Poras T. Balsara (IEEE J. Solid State Circuits, 2011)

Alien crosstalk mitigation in vectored DSL systems for backhaul applications. - Aditya Awasthi; Naofal Al-Dhahir; Oren E. Eliezer; Poras T. Balsara (ICC, 2012)

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management. - Sujan K. Manohar; Vinod K. Somasundar; Ramakrishnan Venkatasubramanian; Poras T. Balsara (VLSI Design, 2012)

Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency. - Sujan K. Manohar; Ramakrishnan Venkatasubramanian; Poras T. Balsara (VLSI Design, 2012)

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops. - Ioannis L. Syllaios; Poras T. Balsara (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Estimation of passive mixer output bandwidth using switched-capacitor techniques. - Essam S. Atalla; Frank Zhang; Abdellatif Bellaouar; Poras T. Balsara (CICC, 2013)

94.6% peak efficiency DCM buck converter with fast adaptive dead-time control. - Sujan K. Manohar; Poras T. Balsara (ESSCIRC, 2013)

Novel analysis of passive mixer output impedance using switched-capacitor techniques. - Essam S. Atalla; Abdellatif Bellaouar; Poras T. Balsara (MWSCAS, 2013)

IIP2 requirements in 4G LTE handset receivers. - Essam S. Atalla; Abdellatif Bellaouar; Poras T. Balsara (MWSCAS, 2013)

Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications. - Aditya Awasthi; Rohit Guttal; Naofal Al-Dhahir; Poras T. Balsara (IEEE Commun. Lett., 2014)

Envelope tracking using transient waveform switching shaping supply modulation. - Sankalp Modi; Poras T. Balsara; Oren E. Eliezer (Int. J. Circuit Theory Appl., 2015)

Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter. - Sujan K. Manohar; L. R. Hunt; Poras T. Balsara; Dinesh K. Bhatia; Vikas V. Paduvalli (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Effect of sampling time and sampling instant on the frequency response of a boost converter. - Sameer Arora; Poras T. Balsara; Dinesh K. Bhatia (IECON, 2016)

A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. - Imran Bashir; Robert Bogdan Staszewski; Oren E. Eliezer; Poras T. Balsara (J. Electron. Test., 2016)

A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution. - Imran Bashir; Robert Bogdan Staszewski; Poras T. Balsara (IEEE J. Solid State Circuits, 2016)

Portable impedance measurement device for sweat based glucose detection. - Athul Asokan Thulasi; Dinesh Bhatia; Poras T. Balsara; Shalini Prasad (BSN, 2017)

Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach. - Essam S. Atalla; Frank Zhang; Poras T. Balsara; Abdellatif Bellaouar; Seydou Ba; Kamran Kiasaleh (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach. - Vikas V. Paduvalli; R. J. Taylor; Poras T. Balsara (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM. - Vikas V. Paduvalli; R. J. Taylor; Louis R. Hunt; Poras T. Balsara (IEEE Trans. Ind. Electron., 2018)

New Concept for Fault Current Limiter With Voltage Restoration Capability. - Hesam Nourmohamadi; Mehran Sabahi; Poras T. Balsara; Ebrahim Babaei; Seyed Hossein Hosseini 002; Amir Fakhim-Babaei (IEEE Trans. Ind. Electron., 2020)

A new submodule structure with parallel capacitor connection in modular multilevel converters. - G. Veera Bharath; Ghanshyamsinh Gohil; Poras T. Balsara (ISCAS, 2022)

Fully Distributed Control of Microgrids Using Multi-Agent Approach. - Vaibhav Uttam Pawaskar; Poras T. Balsara; Babak Fahimi; Ghanshyamsinh Gohil (IECON, 2023)

Adaptive PLL-based Sensorless Control for CSI-Fed PMSM Drives Used in Submersible Pumps. - Milad Bahrami-Fard; Majid Ghasemi Korrani; Mohammad Rastegar; Poras T. Balsara; Babak Fahimi (IECON, 2024)

Bifurcation Analysis under Various Modulation Techniques in PWM-Controlled DC-DC Converters. - Mohammad Hassan Ghaderi; Milad Bahrami-Fard; Nasim Rashidirad; Babak Fahimi; Poras T. Balsara (IECON, 2024)

Dynamic Modeling of a Double-Stator Switched Reluctance Motor (DSSRM) Using a Lumped Parameter Circuit Model. - Behnam Mosammam; Milad Bahrami-Fard; Babak Fahimi; Poras T. Balsara (IECON, 2024)

Hardware-based Detection of Malicious Firmware Modification in Microgrids. - Amisha Srivastava; Sneha Thakur; Abraham Peedikayil Kuruvila; Poras T. Balsara; Kanad Basu (VLSID, 2024)

Intelligent Multi-Functional Fault Current Limiter. - Hesam Nourmohamadi; Ghanshyamsinh Gohil; Poras T. Balsara (IEEE Trans. Smart Grid, 2024)