Equivalence checking of hierarchical combinational circuits. - Poul Frederick Williams; Henrik Hulgaard; Henrik Reif Andersen (ICECS, 1999)

Equivalence checking of combinational circuits using Boolean expression diagrams. - Henrik Hulgaard; Poul Frederick Williams; Henrik Reif Andersen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. - Poul Frederick Williams; Armin Biere; Edmund M. Clarke; Anubhav Gupta 001 (CAV, 2000)

Bypassing BDD construction for reliability analysis. - Poul Frederick Williams; Macha Nikolskaïa; Antoine Rauzy (Inf. Process. Lett., 2000)

Formal Verification based on Boolean Expression Diagrams. - Poul Frederick Williams (Elsevier, 2001)

Satisfiability checking using Boolean Expression Diagrams. - Poul Frederick Williams; Henrik Reif Andersen; Henrik Hulgaard (Int. J. Softw. Tools Technol. Transf., 2003)