Design-Silicon Timing Correlation A Data Mining Perspective. - Li-C. Wang; Pouria Bastani; Magdy S. Abadir (DAC, 2007)

Analyzing the risk of timing modeling based on path delay tests. - Pouria Bastani; Benjamin N. Lee; Li-C. Wang; Savithri Sundareswaran; Magdy S. Abadir (ITC, 2007)

Statistical diagnosis of unmodeled systematic timing effects. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (DAC, 2008)

Speedpath prediction based on learning from a small set of examples. - Pouria Bastani; Kip Killpack; Li-C. Wang; Eli Chiprout (DAC, 2008)

Silicon feedback to improve frequency of high-performance microprocessors: an overview. - Chandramouli V. Kashyap; Pouria Bastani; Kip Killpack; Chirayu S. Amin (ICCAD, 2008)

Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (ITC, 2008)

Linking Statistical Learning to Diagnosis. - Pouria Bastani; Li-C. Wang; Magdy S. Abadir (IEEE Des. Test Comput., 2008)

Case Study on Speed Failure Causes in a Microprocessor. - Kip Killpack; Suriyaprakash Natarajan; Arun Krishnamachary; Pouria Bastani (IEEE Des. Test Comput., 2008)

Path selection for monitoring unexpected systematic timing effects. - Nicholas Callegari; Pouria Bastani; Li-C. Wang; Sreejit Chakravarty; Alexander Tetelbaum (ASP-DAC, 2009)

Speedpath analysis based on hypothesis pruning and ranking. - Nicholas Callegari; Li-C. Wang; Pouria Bastani (DAC, 2009)

Feature based similarity search with application to speedpath analysis. - Nicholas Callegari; Li-C. Wang; Pouria Bastani (ITC, 2009)

A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. - Nicholas Callegari; Pouria Bastani; Li-C. Wang; Magdy S. Abadir (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. - Pouria Bastani; Nicholas Callegari; Li-C. Wang; Magdy S. Abadir (IEEE Des. Test Comput., 2010)