An Analysis of the Economics of Self Test. - Prab Varma; Anthony P. Ambler; Keith Baker (ITC, 1984)

A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. - S. B. Tan; K. Totton; Keith Baker; Prab Varma; R. Porter (DAC, 1987)

A knowledge-based test generator for standard cell and iterative array logic circuits. - Prab Varma; Yoshihiro Tohma (IEEE J. Solid State Circuits, 1988)

TDRC-a symbolic simulation based design for testability rules checker. - Prab Varma (ITC, 1990)

On test generation for path delay faults in ASICs. - Prab Varma (VTS, 1992)

Scan DFT: Why More Can Cost Less. - Prab Varma (ITC, 1993)

Delay Testing Using a Matrix of Accessible Storage. - Prab Varma; Tushar Gheewala (ITC, 1993)

On Path-Delay Testing in a Standard Scan Environment. - Prab Varma (ITC, 1994)

The economics of scan-path design for testability. - Prab Varma; Tushar Gheewala (J. Electron. Test., 1994)

Optimizing Product Profitability - The Test Way. - Prab Varma (ITC, 1995)

A Unifying Methodology for Intellectual Property and Custom Logic Testing. - Sandeep Bhatia; Tushar Gheewala; Prab Varma (ITC, 1996)

Delay Fault Testing: How Robust are Our Models? - Sandeep K. Gupta 001; Slawomir Pilarski; Sudhakar M. Reddy; Jacob Savir; Prab Varma (VTS, 1996)

Test Compaction in a Parallel Access Scan Environment. - Sandeep Bhatia; Prab Varma (Asian Test Symposium, 1997)

System Chip Test Challenges, Are There Solutions Today? (Panel). - Prab Varma (DAC, 1998)

System chip test: are we there yet? - Prab Varma (ITC, 1998)

A structured test re-use methodology for core-based system chips. - Prab Varma; Sandeep Bhatia (ITC, 1998)

Test Cycle Count Reduction in a Parallel Scan BIST Environment. - Bechir Ayari; Prab Varma (J. Electron. Test., 2000)

ATPG for Design Errors-Is It Possible? - Magdy S. Abadir; Scott Davidson 001; Vijay Nagasamy; Dhiraj K. Pradhan; Prab Varma (VTS, 2001)

Design Verification Problems: Test To The Rescue? - Prab Varma (ITC, 2003)

Verification evolution or industrial revolution? - Prab Varma (IEEE Des. Test Comput., 2004)

Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. - Prab Varma (Asian Test Symposium, 2012)

Welcome Message. - Prab Varma; Miroslav N. Velev (HLDVT, 2016)