High-speed and low power unified dual-field multiplier in GF (P) and GF (2m). - Prabhat Chandra Shrivastava; Rupesh Kumar; Arvind Kumar; Sanjeev Rai (APCCAS, 2010)

ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic. - Prashant Kumar; Prabhat Chandra Shrivastava; Manish Tiwari; Amit Dhawan (Circuits Syst. Signal Process., 2018)

High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm. - Prashant Kumar; Prabhat Chandra Shrivastava; Manish Tiwari; Ganga Ram Mishra (Circuits Syst. Signal Process., 2019)

Efficient Architecture for the Realization of 2-D Adaptive FIR Filter Using Distributed Arithmetic. - Prabhat Chandra Shrivastava; Prashant Kumar; Manish Tiwari; Amit Dhawan (Circuits Syst. Signal Process., 2021)

An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method. - Prabhat Chandra Shrivastava; Prashant Kumar; Manish Tiwari; Amit Dhawan (Circuits Syst. Signal Process., 2022)