Automatic validation of pipeline specifications. - Prabhat Mishra 001; Nikil D. Dutt; Alex Nicolau (HLDVT, 2001)

Functional abstraction driven design space exploration of heterogeneous programmable architectures. - Prabhat Mishra 001; Nikil D. Dutt; Alexandru Nicolau (ISSS, 2001)

Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. - Prabhat Mishra 001; Peter Grun; Nikil D. Dutt; Alexandru Nicolau (VLSI Design, 2001)

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. - Prabhat Mishra 001; Nikil D. Dutt; Alexandru Nicolau; Hiroyuki Tomiyama (DATE, 2002)

Automatic functional test program generation for pipelined processors using model checking. - Prabhat Mishra 001; Nikil D. Dutt (HLDVT, 2002)

Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. - Prabhat Mishra 001; Nikil D. Dutt (DIPES, 2002)

Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. - Prabhat Mishra 001; Hiroyuki Tomiyama; Ashok Halambi; Peter Grun; Nikil D. Dutt; Alexandru Nicolau (ASP-DAC/VLSI Design, 2002)

An efficient retargetable framework for instruction-set simulation. - Mehrdad Reshadi; Nikhil Bansal 003; Prabhat Mishra 001; Nikil D. Dutt (CODES+ISSS, 2003)

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. - Mehrdad Reshadi; Prabhat Mishra 001; Nikil D. Dutt (DAC, 2003)

A Methodology for Validation of Microprocessors using Equivalence Checking. - Prabhat Mishra 001; Nikil D. Dutt (MTV, 2003)

Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. - Prabhat Mishra 001; Arun Kejariwal; Nikil D. Dutt (IEEE International Workshop on Rapid System Prototyping, 2003)

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. - Prabhat Mishra 001; Nikil D. Dutt; Hiroyuki Tomiyama (Des. Autom. Embed. Syst., 2003)

Graph-Based Functional Test Program Generation for Pipelined Processors. - Prabhat Mishra 001; Nikil D. Dutt (DATE, 2004)

Functional Validation of Programmable Architectures. - Prabhat Mishra 001; Nikil D. Dutt (DSD, 2004)

Functional Verification of Pipelined Processors: A Case Study. - Prabhat Mishra 001; Nikil D. Dutt; Yaron Kashai (MTV, 2004)

Synthesis-driven Exploration of Pipelined Embedded Processors. - Prabhat Mishra 001; Arun Kejariwal; Nikil D. Dutt (VLSI Design, 2004)

A Top-Down Methodology for Microprocessor Validation. - Prabhat Mishra 001; Nikil D. Dutt; Narayanan Krishnamurthy; Magdy S. Abadir (IEEE Des. Test Comput., 2004)

Modeling and validation of pipeline specifications. - Prabhat Mishra 001; Nikil D. Dutt (ACM Trans. Embed. Comput. Syst., 2004)

Processor-memory coexploration using an architecture description language. - Prabhat Mishra 001; Mahesh Mamidipaka; Nikil D. Dutt (ACM Trans. Embed. Comput. Syst., 2004)

Functional verification of programmable embedded architectures - a top-down approach. - Prabhat Mishra 001; Nikil D. Dutt (Springer, 2005)

Memory access optimizations in instruction-set simulators. - Mehrdad Reshadi; Prabhat Mishra 001 (CODES+ISSS, 2005)

Functional Coverage Driven Test Generation for Validation of Pipelined Processors. - Prabhat Mishra 001; Nikil D. Dutt (DATE, 2005)

Language-driven Validation of Pipelined Processors using Satisfiability Solvers. - Prabhat Mishra 001; Heon-Mo Koo; Zhuo Huang (MTV, 2005)

A methodology for validation of microprocessors using symbolic simulation. - Prabhat Mishra 001; Nikil D. Dutt; Narayanan Krishnamurthy; Magdy S. Abadir (Int. J. Embed. Syst., 2005)

Functional test generation using property decompositions for validation of pipelined processors. - Heon-Mo Koo; Prabhat Mishra 001 (DATE, 2006)

Test generation using SAT-based bounded model checking for validation of pipelined processors. - Heon-Mo Koo; Prabhat Mishra 001 (ACM Great Lakes Symposium on VLSI, 2006)

A bitmask-based code compression technique for embedded systems. - Seok-Won Seong; Prabhat Mishra 001 (ICCAD, 2006)

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. - Heon-Mo Koo; Prabhat Mishra 001; Jayanta Bhadra; Magdy S. Abadir (MTV, 2006)

A retargetable framework for instruction-set architecture simulation. - Mehrdad Reshadi; Nikil D. Dutt; Prabhat Mishra 001 (ACM Trans. Embed. Comput. Syst., 2006)

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. - Prabhat Mishra 001; Aviral Shrivastava; Nikil D. Dutt (ACM Trans. Design Autom. Electr. Syst., 2006)

A Retargetable Software Timing Analyzer Using Architecture Description Language. - Xianfeng Li; Abhik Roychoudhury; Tulika Mitra; Prabhat Mishra 001; Xu Cheng 001 (ASP-DAC, 2007)

An efficient code compression technique using application-aware bitmask and dictionary selection methods. - Seok-Won Seong; Prabhat Mishra 001 (DATE, 2007)

Towards RTL test generation from SystemC TLM specifications. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (HLDVT, 2007)

Specification-based compaction of directed tests for functional validation of pipelined processors. - Heon-Mo Koo; Prabhat Mishra 001 (CODES+ISSS, 2008)

A novel test-data compression technique using application-aware bitmask and dictionary selection methods. - Kanad Basu; Prabhat Mishra 001 (ACM Great Lakes Symposium on VLSI, 2008)

Coverage-driven automatic test generation for uml activity diagrams. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (ACM Great Lakes Symposium on VLSI, 2008)

Bitmask-Based Code Compression for Embedded Systems. - Seok-Won Seong; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Specification-driven directed test generation for validation of pipelined processors. - Prabhat Mishra 001; Nikil D. Dutt (ACM Trans. Design Autom. Electr. Syst., 2008)

Generating test programs to cover pipeline interactions. - Thanh Nga Dang; Abhik Roychoudhury; Tulika Mitra; Prabhat Mishra 001 (DAC, 2009)

Bitmask-based control word compression for NISC architectures. - Chetan Murthy; Prabhat Mishra 001 (ACM Great Lakes Symposium on VLSI, 2009)

Chairs' welcome message. - Priyank Kalla; Prabhat Mishra 001 (HLDVT, 2009)

Lossless Compression Using Efficient Encoding of Bitmasks. - Chetan Murthy; Prabhat Mishra 001 (ISVLSI, 2009)

Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems. - Weixun Wang; Prabhat Mishra 001 (ISVLSI, 2009)

Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. - Prabhat Mishra 001; Mingsong Chen 001 (VLSI Design, 2009)

Efficient Placement of Compressed Code for Parallel Decompression. - Xiaoke Qin; Prabhat Mishra 001 (VLSI Design, 2009)

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. - Weixun Wang; Prabhat Mishra 001; Ann Gordon-Ross (VLSI Design, 2009)

Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures. - Prabhat Mishra 001 (Int. J. Parallel Program., 2009)

A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression. - Xiaoke Qin; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Functional test generation using design and property decomposition techniques. - Heon-Mo Koo; Prabhat Mishra 001 (ACM Trans. Embed. Comput. Syst., 2009)

Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. - Mehrdad Reshadi; Prabhat Mishra 001; Nikil D. Dutt (ACM Trans. Embed. Comput. Syst., 2009)

PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. - Weixun Wang; Prabhat Mishra 001 (DAC, 2010)

Efficient decision ordering techniques for SAT-based test generation. - Mingsong Chen 001; Xiaoke Qin; Prabhat Mishra 001 (DATE, 2010)

Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. - Weixun Wang; Xiaoke Qin; Prabhat Mishra 001 (ISLPED, 2010)

Synchronized Generation of Directed Tests Using Satisfiability Solving. - Xiaoke Qin; Mingsong Chen 001; Prabhat Mishra 001 (VLSI Design, 2010)

Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. - Weixun Wang; Prabhat Mishra 001 (VLSI Design, 2010)

Efficient test case generation for validation of UML activity diagrams. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (Des. Autom. Embed. Syst., 2010)

Guest Editorial. - Prabhat Mishra 001 (J. Electron. Test., 2010)

Functional Test Generation Using Efficient Property Clustering and Learning Techniques. - Mingsong Chen 001; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods. - Kanad Basu; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. - Weixun Wang; Prabhat Mishra 001; Sanjay Ranka (DAC, 2011)

Decision ordering based property decomposition for functional test generation. - Mingsong Chen 001; Prabhat Mishra 001 (DATE, 2011)

Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems. - Hadi Hajimiri; Kamran Rahmani; Prabhat Mishra 001 (IGCC, 2011)

Efficient directed test generation for validation of multicore architectures. - Xiaoke Qin; Prabhat Mishra 001 (ISQED, 2011)

Efficient combination of trace and scan signals for post silicon validation and debug. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (ITC, 2011)

Efficient Trace Signal Selection for Post Silicon Validation and Debug. - Kanad Basu; Prabhat Mishra 001 (VLSI Design, 2011)

Dual Code Compression for Embedded Systems. - Kartik Shrivastava; Prabhat Mishra 001 (VLSI Design, 2011)

A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems. - Weixun Wang; Sanjay Ranka; Prabhat Mishra 001 (VLSI Design, 2011)

Efficient trace data compression using statically selected dictionary. - Kanad Basu; Prabhat Mishra 001 (VTS, 2011)

Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. - Prabhat Mishra 001; Zeljko Zilic; Sandeep K. Shukla (IEEE Des. Test Comput., 2011)

A Brief History of Multiprocessors and EDA. - Sandeep K. Shukla; Prabhat Mishra 001; Zeljko Zilic (IEEE Des. Test Comput., 2011)

Challenges of Rapidly Emerging Consumer Space Multiprocessors. - Zeljko Zilic; Prabhat Mishra 001; Sandeep K. Shukla (IEEE Des. Test Comput., 2011)

Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems. - Weixun Wang; Prabhat Mishra 001 (J. Low Power Electron., 2011)

Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems. - Weixun Wang; Sanjay Ranka; Prabhat Mishra 001 (Sustain. Comput. Informatics Syst., 2011)

Property Learning Techniques for Efficient Generation of Directed Tests. - Mingsong Chen 001; Prabhat Mishra 001 (IEEE Trans. Computers, 2011)

Decoding-Aware Compression of FPGA Bitstreams. - Xiaoke Qin; Chetan Muthry; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Automated generation of directed tests for transition coverage in cache coherence protocols. - Xiaoke Qin; Prabhat Mishra 001 (DATE, 2012)

Synergistic integration of code encryption and compression in embedded systems. - Kamran Rahmani; Hadi Hajimiri; Kartik Shrivastava; Prabhat Mishra 001 (ACM Great Lakes Symposium on VLSI, 2012)

Memory-based computing for performance and energy improvement in multicore architectures. - Kamran Rahmani; Prabhat Mishra 001; Swarup Bhunia (ACM Great Lakes Symposium on VLSI, 2012)

Constrained signal selection for post-silicon validation. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (HLDVT, 2012)

Intra-Task Dynamic Cache Reconfiguration. - Hadi Hajimiri; Prabhat Mishra 001 (VLSI Design, 2012)

Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems. - Zhe Wang 059; Sanjay Ranka; Prabhat Mishra 001 (VLSI Design, 2012)

Compression-aware dynamic cache reconfiguration for embedded systems. - Hadi Hajimiri; Kamran Rahmani; Prabhat Mishra 001 (Sustain. Comput. Informatics Syst., 2012)

Energy-aware dynamic slack allocation for real-time multitasking systems. - Weixun Wang; Sanjay Ranka; Prabhat Mishra 001 (Sustain. Comput. Informatics Syst., 2012)

TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems. - Xiaoke Qin; Weixun Wang; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Automatic RTL Test Generation from SystemC TLM Specifications. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (ACM Trans. Embed. Comput. Syst., 2012)

Dynamic Cache Reconfiguration for Soft Real-Time Systems. - Weixun Wang; Prabhat Mishra 001; Ann Gordon-Ross (ACM Trans. Embed. Comput. Syst., 2012)

Directed test generation for validation of multicore architectures. - Xiaoke Qin; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. - Weixun Wang; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Energy-Aware Scheduling and Dynamic Reconfiguration in Real-Time Systems. - Weixun Wang; Xiaoke Qin; Prabhat Mishra 001 (Handbook of Energy-Aware and Green Computing, 2012)

Scalable trace signal selection using machine learning. - Kamran Rahmani; Prabhat Mishra 001; Sandip Ray (ICCD, 2013)

Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning. - Mingsong Chen 001; Saijie Huang; Geguang Pu; Prabhat Mishra 001 (ISVLSI, 2013)

Dynamic Selection of Trace Signals for Post-Silicon Debug. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra; Amir Nahir; Allon Adir (MTV, 2013)

Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory. - Hadi Hajimiri; Prabhat Mishra 001; Swarup Bhunia; Branden Long; Yibo Li; Rashmi Jha (NANOARCH, 2013)

Proactive thermal management using memory based computing. - Hadi Hajimiri; Mimonah Al Qathrady; Prabhat Mishra 001 (NANOARCH, 2013)

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (VLSI Design, 2013)

Assertion-Based Functional Consistency Checking between TLM and RTL Models. - Mingsong Chen 001; Prabhat Mishra 001 (VLSI Design, 2013)

Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures. - Hadi Hajimiri; Prabhat Mishra 001; Swarup Bhunia (VLSI Design, 2013)

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. - Prabhat Mishra 001; Masahiro Fujita; Virendra Singh; Nagesh Tamarapalli; Sharad Kumar; Rajesh Mittal (VLSI Design, 2013)

Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers. - Kamran Rahmani; Prabhat Mishra 001 (VLSI Design, 2013)

Bitmask aware compression of NISC control words. - Kanad Basu; Chetan Murthy; Prabhat Mishra 001 (Integr., 2013)

RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation. - Kanad Basu; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Directed test generation for hybrid systems. - Sudhi Proch; Prabhat Mishra 001 (ISQED, 2014)

Efficient trace signal selection using augmentation and ILP techniques. - Kamran Rahmani; Prabhat Mishra 001; Sandip Ray (ISQED, 2014)

Layout-Aware Selection of Trace Signals for Post-Silicon Debug. - Prateek Thakyal; Prabhat Mishra 001 (ISVLSI, 2014)

Layout-aware signal selection in reconfigurable architectures. - Prateek Thakyal; Prabhat Mishra 001 (VDAT, 2014)

Scalable Test Generation by Interleaving Concrete and Symbolic Execution. - Xiaoke Qin; Prabhat Mishra 001 (VLSID, 2014)

TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems. - Xiaoke Qin; Prabhat Mishra 001 (VLSID, 2014)

Learning-oriented Property Decomposition for Automated Generation of Directed Tests. - Mingsong Chen 001; Xiaoke Qin; Prabhat Mishra 001 (J. Electron. Test., 2014)

Pre-silicon security verification and validation: a formal perspective. - Xiaolong Guo; Raj Gautam Dutta; Yier Jin; Farimah Farahmandi; Prabhat Mishra 001 (DAC, 2015)

Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking. - Mingsong Chen 001; Daian Yue; Xiaoke Qin; Xin Fu; Prabhat Mishra 001 (DATE, 2015)

Trace Buffer Attack: Security versus observability study in post-silicon debug. - Yuanwen Huang; Anupam Chattopadhyay; Prabhat Mishra 001 (VLSI-SoC, 2015)

Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis. - Hadi Hajimiri; Kamran Rahmani; Prabhat Mishra 001 (VLSID, 2015)

Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. - Prabhat Mishra 001; Swarup Bhunia; Srivaths Ravi 001 (VLSID, 2015)

MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection. - Yuanwen Huang; Swarup Bhunia; Prabhat Mishra 001 (CCS, 2016)

Automated test generation for Debugging arithmetic circuits. - Farimah Farahmandi; Prabhat Mishra 001 (DATE, 2016)

Exploiting transaction level models for observability-aware post-silicon test generation. - Farimah Farahmandi; Prabhat Mishra 001; Sandip Ray (DATE, 2016)

Scalable SoC trust verification using integrated theorem proving and model checking. - Xiaolong Guo; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (HOST, 2016)

Reliability and energy-aware cache reconfiguration for embedded systems. - Yuanwen Huang; Prabhat Mishra 001 (ISQED, 2016)

Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. - Xiaolong Guo; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (MTV, 2016)

Test Generation for Hybrid Systems Using Clustering and Learning Techniques. - Sudhi Proch; Prabhat Mishra 001 (VLSID, 2016)

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques. - Mingsong Chen 001; Xinqian Zhang; Geguang Pu; Xin Fu; Prabhat Mishra 001 (IEEE Trans. Computers, 2016)

Efficient Selection of Trace and Scan Signals for Post-Silicon Debug. - Kamran Rahmani; Sudhi Proch; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Trojan localization using symbolic algebra. - Farimah Farahmandi; Yuanwen Huang; Prabhat Mishra 001 (ASP-DAC, 2017)

Cost-effective analysis of post-silicon functional coverage events. - Farimah Farahmandi; Ronny Morad; Avi Ziv; Ziv Nevo; Prabhat Mishra 001 (DATE, 2017)

QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models. - Alif Ahmed; Prabhat Mishra 001 (ICCD, 2017)

Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction. - Farimah Farahmandi; Prabhat Mishra 001 (ICCD, 2017)

FSM Anomaly Detection Using Formal Analysis. - Farimah Farahmandi; Prabhat Mishra 001 (ICCD, 2017)

Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems. - Yuanwen Huang; Prabhat Mishra 001 (ICCD, 2017)

Post-Silicon Validation in the SoC Era: A Tutorial Introduction. - Prabhat Mishra 001; Ronny Morad; Avi Ziv; Sandip Ray (IEEE Des. Test, 2017)

Trace Buffer Attack on the AES Cipher. - Yuanwen Huang; Prabhat Mishra 001 (J. Hardw. Syst. Secur., 2017)

DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs. - Ujjwal Gupta; Chetan Arvind Patil; Ganapati Bhat; Prabhat Mishra 001; Ümit Y. Ogras (ACM Trans. Embed. Comput. Syst., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. - Xiaolong Guo; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Postsilicon Trace Signal Selection Using Machine Learning Techniques. - Kamran Rahmani; Sandip Ray; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Directed test generation using concolic testing on RTL models. - Alif Ahmed; Farimah Farahmandi; Prabhat Mishra 001 (DATE, 2018)

An automated configurable Trojan insertion framework for dynamic trust benchmarks. - Jonathan Cruz 001; Yuanwen Huang; Prabhat Mishra 001; Swarup Bhunia (DATE, 2018)

Proactive Thermal Management using Memory-based Computing in Multicore Architectures. - Subodha Charles; Hadi Hajimiri; Prabhat Mishra 001 (IGSC, 2018)

Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution. - Alif Ahmed; Farimah Farahmandi; Yousef Iskander; Prabhat Mishra 001 (ITC, 2018)

Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs. - Subodha Charles; Chetan Arvind Patil; Ümit Y. Ogras; Prabhat Mishra 001 (NOCS, 2018)

Hardware Trojan Detection Using ATPG and Model Checking. - Jonathan Cruz 001; Farimah Farahmandi; Alif Ahmed; Prabhat Mishra 001 (VLSID, 2018)

A Survey of Side-Channel Attacks on Caches and Countermeasures. - Yangdi Lyu; Prabhat Mishra 001 (J. Hardw. Syst. Secur., 2018)

Scalable Test Generation for Trojan Detection Using Side Channel Analysis. - Yuanwen Huang; Swarup Bhunia; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2018)

Security and Trust Verification of IoT SoCs. - Alif Ahmed; Farimah Farahmandi; Yousef Iskander; Prabhat Mishra 001 (Security and Fault Tolerance in Internet of Things, 2019)

The Metric Matters: The Art of Measuring Trust in Electronics. - Jonathan Cruz 001; Prabhat Mishra 001; Swarup Bhunia (DAC, 2019)

Real-time Detection and Localization of DoS Attacks in NoC based SoCs. - Subodha Charles; Yangdi Lyu; Prabhat Mishra 001 (DATE, 2019)

Automated Activation of Multiple Targets in RTL Models using Concolic Testing. - Yangdi Lyu; Alif Ahmed; Prabhat Mishra 001 (DATE, 2019)

Efficient Test Generation for Trojan Detection using Side Channel Analysis. - Yangdi Lyu; Prabhat Mishra 001 (DATE, 2019)

Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits. - Farimah Farahmandi; Prabhat Mishra 001 (IEEE Trans. Computers, 2019)

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems. - Yuanwen Huang; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Directed Test Generation for Validation of Cache Coherence Protocols. - Yangdi Lyu; Xiaoke Qin; Mingsong Chen 001; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks. - Adib Nahiyan; Farimah Farahmandi; Prabhat Mishra 001; Domenic Forte; Mark Tehranipoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization. - Alif Ahmed; Yuanwen Huang; Prabhat Mishra 001 (ACM Trans. Embed. Comput. Syst., 2019)

Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs. - Subodha Charles; Alif Ahmed; Ümit Y. Ogras; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics. - Prabhat Mishra 001; Debdeep Mukhopadhyay; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Automated Test Generation for Activation of Assertions in RTL Models. - Yangdi Lyu; Prabhat Mishra 001 (ASP-DAC, 2020)

Automated Trigger Activation by Repeated Maximal Clique Sampling. - Yangdi Lyu; Prabhat Mishra 001 (ASP-DAC, 2020)

Lightweight Anonymous Routing in NoC based SoCs. - Subodha Charles; Megan Logan; Prabhat Mishra 001 (DATE, 2020)

Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis. - Yangdi Lyu; Prabhat Mishra 001 (DATE, 2020)

Test Generation using Reinforcement Learning for Delay-based Side-Channel Analysis. - Zhixin Pan; Jennifer Sheldon; Prabhat Mishra 001 (ICCAD, 2020)

Hardware-Assisted Malware Detection using Explainable Machine Learning. - Zhixin Pan; Jennifer Sheldon; Prabhat Mishra 001 (ICCD, 2020)

Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum Systems. - Daniel Volya; Prabhat Mishra 001 (ICCD, 2020)

Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches. - Yuanwen Huang; Prabhat Mishra 001 (ISQED, 2020)

Lightweight and Trust-Aware Routing in NoC-Based SoCs. - Subodha Charles; Prabhat Mishra 001 (ISVLSI, 2020)

Securing Network-on-Chip Using Incremental Cryptography. - Subodha Charles; Prabhat Mishra 001 (ISVLSI, 2020)

SECTAR: Secure NoC using Trojan Aware Routing. - Manju Rajan; Abhijit Das 002; John Jose; Prabhat Mishra 001 (NOCS, 2020)

System-on-Chip Security Assertions. - Yangdi Lyu; Prabhat Mishra 001 (CoRR, 2020)

Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs. - Subodha Charles; Yangdi Lyu; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning. - Kamran Rahmani; Prabhat Mishra 001 (IEEE Trans. Emerg. Top. Comput., 2020)

Reconfigurable Network-on-Chip Security Architecture. - Subodha Charles; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2020)

Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning. - Zhixin Pan; Prabhat Mishra 001 (ASP-DAC, 2021)

Quantum Spectral Clustering of Mixed Graphs. - Daniel Volya; Prabhat Mishra 001 (DAC, 2021)

Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks. - Meenu Rani Dey; Moumita Patra; Prabhat Mishra 001 (DATE, 2021)

Hardware-Assisted Malware Detection using Machine Learning. - Zhixin Pan; Jennifer Sheldon; Chamika Sudusinghe; Subodha Charles; Prabhat Mishra 001 (DATE, 2021)

Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning. - Zhixin Pan; Prabhat Mishra 001 (HOST, 2021)

Lightweight Encryption Using Chaffing and Winnowing with All-or-Nothing Transform for Network-on-Chip Architectures. - Hansika Weerasena; Subodha Charles; Prabhat Mishra 001 (HOST, 2021)

Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks. - Zhixin Pan; Prabhat Mishra 001 (ISVLSI, 2021)

Denial-of-service attack detection using machine learning in network-on-chip architectures. - Chamika Sudusinghe; Subodha Charles; Prabhat Mishra 001 (NOCS, 2021)

Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems. - Abhijit Das 002; John Jose; Prabhat Mishra 001 (CoRR, 2021)

Hardware Acceleration of Explainable Machine Learning using Tensor Processing Units. - Zhixin Pan; Prabhat Mishra 001 (CoRR, 2021)

Fast Approximate Spectral Normalization for Robust Deep Neural Networks. - Zhixin Pan; Prabhat Mishra 001 (CoRR, 2021)

Scalable Concolic Testing of RTL Models. - Yangdi Lyu; Prabhat Mishra 001 (IEEE Trans. Computers, 2021)

Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling. - Yangdi Lyu; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns. - Yangdi Lyu; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2021)

Directed Test Generation for Activation of Security Assertions in RTL Models. - Hasini Witharana; Yangdi Lyu; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2021)

Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems. - Abhijit Das 002; John Jose; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans. - Zhixin Pan; Prabhat Mishra 001 (DATE, 2022)

Hardware Acceleration of Explainable Machine Learning. - Zhixin Pan; Prabhat Mishra 001 (DATE, 2022)

Speculative Load Forwarding Attack on Modern Processors. - Hasini Witharana; Prabhat Mishra 001 (ICCAD, 2022)

Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks. - Aruna Jayasena; Khushboo Rani; Prabhat Mishra 001 (ICCD, 2022)

Modeling of Noisy Quantum Circuits using Random Matrix Theory. - Daniel Volya; Prabhat Mishra 001 (ICCD, 2022)

A Survey on Hardware Vulnerability Analysis Using Machine Learning. - Zhixin Pan; Prabhat Mishra 001 (IEEE Access, 2022)

Backdoor Attacks on Bayesian Neural Networks using Reverse Distribution. - Zhixin Pan; Prabhat Mishra 001 (CoRR, 2022)

A Survey of Network-on-Chip Security Attacks and Countermeasures. - Subodha Charles; Prabhat Mishra 001 (ACM Comput. Surv., 2022)

Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures. - Chamika Sudusinghe; Subodha Charles; Sapumal Ahangama; Prabhat Mishra 001 (IEEE Des. Test, 2022)

Secure Register Allocation for Trusted Code Generation. - Priyanka Panigrahi; Vemuri Sahithya; Chandan Karfa; Prabhat Mishra 001 (IEEE Embed. Syst. Lett., 2022)

Network-on-Chip Trust Validation Using Security Assertions. - Aruna Jayasena; Binod Kumar; Subodha Charles; Hasini Witharana; Prabhat Mishra 001 (J. Hardw. Syst. Secur., 2022)

Hardware-Assisted Malware Detection and Localization Using Explainable Machine Learning. - Zhixin Pan; Jennifer Sheldon; Prabhat Mishra 001 (IEEE Trans. Computers, 2022)

Data Perturbation and Recovery of Time Series Gene Expression Data. - Aisharjya Sarkar; Prabhat Mishra 001; Tamer Kahveci (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures. - Subodha Charles; Vincent Bindschaedler; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Survey on Assertion-based Hardware Verification. - Hasini Witharana; Yangdi Lyu; Subodha Charles; Prabhat Mishra 001 (ACM Comput. Surv., 2022)

Hardware Trojan Detection Using Shapley Ensemble Boosting. - Zhixin Pan; Prabhat Mishra 001 (ASP-DAC, 2023)

Quantum Data Compression for Efficient Generation of Control Pulses. - Daniel Volya; Prabhat Mishra 001 (ASP-DAC, 2023)

Quantum Measurement Discrimination using Cumulative Distribution Functions. - Zachery Utt; Daniel Volya; Prabhat Mishra 001 (DATE, 2023)

Dynamic Refinement of Hardware Assertion Checkers. - Hasini Witharana; Sahan Sanjaya; Prabhat Mishra 001 (DATE, 2023)

Towards Secure Classical-Quantum Systems. - Daniel Volya; Tao Zhang 108; Nashmin Alam; Mark Tehranipoor; Prabhat Mishra 001 (HOST, 2023)

Quantum Steering of Surface Error Correcting Codes. - Daniel Volya; Prabhat Mishra 001 (QCE, 2023)

Feedback-Based Steering for Quantum State Preparation. - Daniel Volya; Zhixin Pan; Prabhat Mishra 001 (QCE, 2023)

Lightweight Encryption and Anonymous Routing in NoC based SoCs. - Subodha Charles; Prabhat Mishra 001 (CoRR, 2023)

DETER: Design for Trust utilizing Rareness Reduction. - Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2023)

Sequence-Based Incremental Concolic Testing of RTL Models. - Hasini Witharana; Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2023)

quAssert: Automatic Generation of Quantum Assertions. - Hasini Witharana; Daniel Volya; Prabhat Mishra 001 (CoRR, 2023)

Modeling and Exploration of Gain Competition Attacks in Optical Network-on-Chip Architectures. - Khushboo Rani; Hansika Weerasena; Stephen A. Butler; Subodha Charles; Prabhat Mishra 001 (CoRR, 2023)

Hardware Acceleration of Explainable Artificial Intelligence. - Zhixin Pan; Prabhat Mishra 001 (CoRR, 2023)

Logic Locking based Trojans: A Friend Turns Foe. - Yuntao Liu 001; Aruna Jayasena; Prabhat Mishra 001; Ankur Srivastava 001 (CoRR, 2023)

Breaking NoC Anonymity using Flow Correlation Attack. - Hansika Weerasena; Zhixin Pan; Khushboo Rani; Prabhat Mishra 001 (CoRR, 2023)

QudCom: Towards Quantum Compilation for Qudit Systems. - Daniel Volya; Prabhat Mishra 001 (CoRR, 2023)

Automated Generation of Security Assertions for RTL Models. - Hasini Witharana; Aruna Jayasena; Andrew Whigham; Prabhat Mishra 001 (ACM J. Emerg. Technol. Comput. Syst., 2023)

Efficient Detection and Localization of DoS Attacks in Heterogeneous Vehicular Networks. - Meenu Rani Dey; Moumita Patra; Prabhat Mishra 001 (IEEE Trans. Veh. Technol., 2023)

TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms. - Aruna Jayasena; Emma Andrews; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

QcAssert: Quantum Device Testing with Concurrent Assertions. - Hasini Witharana; Daniel Volya; Prabhat Mishra 001 (ASPDAC, 2024)

EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves. - Aruna Jayasena; Richard Bachmann; Prabhat Mishra 001 (DATE, 2024)

Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments. - Hasini Witharana; Debapriya Chatterjee; Prabhat Mishra 001 (HOST, 2024)

Lightweight Multicast Authentication in NoC-based SoCs. - Hansika Weerasena; Prabhat Mishra 001 (ISQED, 2024)

Variational Quantum Algorithms via Measurement-Induced Passive Steering. - Sahan Sanjaya; Daniel Volya; Prabhat Mishra 001 (QCE, 2024)

Quantum Benchmarking via Random Dynamical Quantum Maps. - Daniel Volya; Prabhat Mishra 001 (QCE, 2024)

Fast Quantum Characterization via Riemannian Optimization. - Daniel Volya; Andrey Nikitin; Prabhat Mishra 001 (QCE, 2024)

Design for Trust Utilizing Rareness Reduction. - Aruna Jayasena; Prabhat Mishra 001 (VLSID, 2024)

Privacy-Preserving Debiasing using Data Augmentation and Machine Unlearning. - Zhixin Pan; Emma Andrews; Laura Chang; Prabhat Mishra 001 (CoRR, 2024)

Fast Quantum Process Tomography via Riemannian Gradient Descent. - Daniel Volya; Andrey Nikitin; Prabhat Mishra 001 (CoRR, 2024)

Explainable Metric Learning for Deflating Data Bias. - Emma Andrews; Prabhat Mishra 001 (CoRR, 2024)

Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers. - Sahan Sanjaya; Hasini Witharana; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey. - Hansika Weerasena; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

Directed Test Generation for Hardware Validation: A Survey. - Aruna Jayasena; Prabhat Mishra 001 (ACM Comput. Surv., 2024)

Incremental Concolic Testing of Register-Transfer Level Designs. - Hasini Witharana; Aruna Jayasena; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

TD-Zero: Automatic Golden-Free Hardware Trojan Detection Using Zero-Shot Learning. - Zhixin Pan; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Breaking On-Chip Communication Anonymity Using Flow Correlation Attacks. - Hansika Weerasena; Prabhat Mishra 001 (ACM J. Emerg. Technol. Comput. Syst., 2024)

HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Formal Verification of Virtualization-Based Trusted Execution Environments. - Hasini Witharana; Hansika Weerasena; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators. - Hansika Weerasena; Prabhat Mishra 001 (ACM Trans. Embed. Comput. Syst., 2024)

Security Assertions for Trusted Execution Environments. - Hasini Witharana; Hansika Weerasena; Prabhat Mishra 001 (DATE, 2025)

Traffic Analysis Attacks on Wireless NoC-Based SoCs. - Hansika Weerasena; Prabhat Mishra 001 (HOST, 2025)

Adversarial Assertions. - Prabhat Mishra 001 (ISQED, 2025)

Formal verification of bioinformatics software using model checking and theorem proving. - Hansika Weerasena; Aruna Jayasena; Christina Boucher 001; Prabhat Mishra 001 (Briefings Bioinform., 2025)

CiseLeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes. - Aruna Jayasena; Richard Bachmann; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2025)

FirmWall: Directed Symbolic Execution of Firmware Binaries for Defending Against Unauthorized System Calls. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2025)

AI Trojan Attack for Evading Machine Learning-Based Detection of Hardware Trojans. - Zhixin Pan; Prabhat Mishra 001 (IEEE Trans. Computers, 2025)

Topology-aware Detection and Localization of Distributed Denial-of-Service Attacks in Network-on-Chips. - Hansika Weerasena; Xiaoguo Jia; Prabhat Mishra 001 (CoRR, 2025)

Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability. - Sahan Sanjaya; Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks. - Sahan Sanjaya; Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2025)