Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (ISED, 2011)

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (Microelectron. J., 2011)

Design of High Speed Vedic Multiplier for Decimal Number System. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (VDAT, 2012)

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. - Prabir Saha; Deepak Kumar; Partha Bhattacharyya; Anup Dandapat (ISED, 2013)

Improved matrix multiplier design for high-speed digital signal processing applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (IET Circuits Devices Syst., 2014)

Design of 64-Bit Squarer Based on Vedic Mathematics. - Prabir Saha; Deepak Kumar; Partha Bhattacharyya; Anup Dandapat (J. Circuits Syst. Comput., 2014)

Integer division technique for signal processing applications. - Deepak Kumar; Abhijit Sharma; Prabir Saha (IMCOM, 2015)

Implementation of high speed processor for computing convolution sum for DSP applications. - Prabir Saha; Deepak Kumar; Abhijit Sharma (IMCOM, 2015)

Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime. - Rekib Uddin Ahmed; Prabir Saha (iNIS, 2017)

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation. - Rekib Uddin Ahmed; Prabir Saha (Period. Polytech. Electr. Eng. Comput. Sci., 2020)

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder. - Sheba Diamond Thabah; Prabir Saha (Period. Polytech. Electr. Eng. Comput. Sci., 2020)

New design approaches of reversible BCD encoder using Peres and Feynman gates. - Sheba Diamond Thabah; Prabir Saha (ICT Express, 2020)

Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication. - Srikant Kumar Beura; Gudmalwar Ashishkumar Prabhakar; Sudesna Manjari Mahanta; Bishnulatpam Pushpa Devi; Prabir Saha (ICCCNT, 2021)

Improved Signed Binary Multiplier Through New Partial Product Generation Scheme. - Sheba Diamond Thabah; Prabir Saha (J. Circuits Syst. Comput., 2021)

Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier. - Sheba Diamond Thabah; Prabir Saha (J. Circuits Syst. Comput., 2022)

VLSI Implementation of Edge Detection Chip: A Prospective Design. - Harsh Raj Thakur; Prabir Saha (iSES, 2024)

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication. - Srikant Kumar Beura; Sudeshna Manjari Mahanta; Bishnulatpam Pushpa Devi; Prabir Saha (Integr., 2024)

Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. - Srikant Kumar Beura; Bishnulatpam Pushpa Devi; Prabir Saha; Pramod Kumar Meher (Circuits Syst. Signal Process., 2024)