A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process. - Abhirup Lahiri; Nitin Gupta; Anand Kumar; Pradeep Dhadda (ESSCIRC, 2014)

A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process. - Abhirup Lahiri; Nitin Gupta; Anand Kumar; Pradeep Dhadda (IEEE J. Solid State Circuits, 2015)