A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. - Pradeep Shettigar; Shanthi Pavan (ISSCC, 2012)

Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs. - Pradeep Shettigar; Shanthi Pavan (IEEE J. Solid State Circuits, 2012)

A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer. - Guowen Wei; Pradeep Shettigar; Feng Su; Xinyu Yu; Tom Kwan (VLSIC, 2015)